FPGA_Uni/tests/instruction_classifier_tb.sv at 60e5dae43bf61b1585ae15c7233b30630f9da141 - FPGA_Uni - Riley's Git Server

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riley a89a66d34d

Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

2026-09-03 16:32:56 +10:00

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Systemverilog

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`#include "instruction_classifier.sv"