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FPGA_Uni/Quartus/A2/output_files/assignment2.sta.summary
T
TroubleElectrical d962a1b557 Added code to display current PC,
Removed Blanking from 7seg 4 digits,
Changed reset to a switch rather than button
Compiled working version for board
2026-10-16 14:27:29 +11:00

54 lines
1.2 KiB
Plaintext

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Timing Analyzer Summary
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Type : Slow 1100mV 85C Model Setup 'clk[0]'
Slack : -14.881
TNS : -27730.277
Type : Slow 1100mV 85C Model Hold 'clk[0]'
Slack : 0.262
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk[0]'
Slack : -0.538
TNS : -1978.741
Type : Slow 1100mV 0C Model Setup 'clk[0]'
Slack : -14.540
TNS : -27019.196
Type : Slow 1100mV 0C Model Hold 'clk[0]'
Slack : 0.245
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk[0]'
Slack : -0.538
TNS : -2025.649
Type : Fast 1100mV 85C Model Setup 'clk[0]'
Slack : -7.846
TNS : -13963.900
Type : Fast 1100mV 85C Model Hold 'clk[0]'
Slack : 0.135
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk[0]'
Slack : 0.016
TNS : 0.000
Type : Fast 1100mV 0C Model Setup 'clk[0]'
Slack : -6.879
TNS : -12147.650
Type : Fast 1100mV 0C Model Hold 'clk[0]'
Slack : 0.123
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk[0]'
Slack : 0.015
TNS : 0.000
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