This website requires JavaScript.
Explore
Help
Sign In
TroubleElectrical
/
FPGA_Uni
Watch
1
Star
0
Fork
0
Code
Issues
1
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
Files
5eb78e92e9ceb7a2eb221b11321115853ca838bf
FPGA_Uni
/
Quartus
/
A1_Q3
/
asu.qws
T
TroubleElectrical
9e5fb6f52b
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
686 B
Raw
History
View Raw
Reference in new issue
View Git Blame
Copy Permalink