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5d9e7f541e0fa318a9db3e263bbf85623aeaeb19
FPGA_Uni
/
Quartus
/
A2
T
History
TroubleElectrical
5d9e7f541e
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
..
db
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
incremental_db
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
output_files
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
simulation
/questa
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
assignment2.qpf
Made Assignment 2 Quartus Project
2026-10-13 12:04:49 +11:00
assignment2.qsf
TODO: Remove Shifter Code
2026-10-13 16:57:03 +11:00
assignment2.qws
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
c5_pin_model_dump.txt
Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)
2026-10-13 13:24:44 +11:00