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FPGA_Uni/Quartus/A2/db/assignment2.hier_info
T
TroubleElectrical 25a953cdc6 Added 4 digit 7seg display module (confirmed working for now), 
Added Inputs for displaying registers / Program Counter high and low bits,
Assigned pins for Display digits, inputs (Labeled HID) and the clk button
2026-10-13 16:32:15 +11:00

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|assignment2
clk[0] => clk[0].IN2
HID_Register[0] => ~NO_FANOUT~
HID_Register[1] => ~NO_FANOUT~
HID_Register[2] => ~NO_FANOUT~
HID_Register[3] => ~NO_FANOUT~
HID_Register[4] => ~NO_FANOUT~
HID_PC[0] => ~NO_FANOUT~
HID_Hi_Low[0] => ~NO_FANOUT~
out_seg_0[0] << seven_seg_4digit:display.segments0
out_seg_0[1] << seven_seg_4digit:display.segments0
out_seg_0[2] << seven_seg_4digit:display.segments0
out_seg_0[3] << seven_seg_4digit:display.segments0
out_seg_0[4] << seven_seg_4digit:display.segments0
out_seg_0[5] << seven_seg_4digit:display.segments0
out_seg_0[6] << seven_seg_4digit:display.segments0
out_seg_0[7] << seven_seg_4digit:display.segments0
out_seg_1[0] << seven_seg_4digit:display.segments1
out_seg_1[1] << seven_seg_4digit:display.segments1
out_seg_1[2] << seven_seg_4digit:display.segments1
out_seg_1[3] << seven_seg_4digit:display.segments1
out_seg_1[4] << seven_seg_4digit:display.segments1
out_seg_1[5] << seven_seg_4digit:display.segments1
out_seg_1[6] << seven_seg_4digit:display.segments1
out_seg_1[7] << seven_seg_4digit:display.segments1
out_seg_2[0] << seven_seg_4digit:display.segments2
out_seg_2[1] << seven_seg_4digit:display.segments2
out_seg_2[2] << seven_seg_4digit:display.segments2
out_seg_2[3] << seven_seg_4digit:display.segments2
out_seg_2[4] << seven_seg_4digit:display.segments2
out_seg_2[5] << seven_seg_4digit:display.segments2
out_seg_2[6] << seven_seg_4digit:display.segments2
out_seg_2[7] << seven_seg_4digit:display.segments2
out_seg_3[0] << seven_seg_4digit:display.segments3
out_seg_3[1] << seven_seg_4digit:display.segments3
out_seg_3[2] << seven_seg_4digit:display.segments3
out_seg_3[3] << seven_seg_4digit:display.segments3
out_seg_3[4] << seven_seg_4digit:display.segments3
out_seg_3[5] << seven_seg_4digit:display.segments3
out_seg_3[6] << seven_seg_4digit:display.segments3
out_seg_3[7] << seven_seg_4digit:display.segments3
|assignment2|instruction_counter:PC
clk[0] => pc[0].CLK
clk[0] => pc[1].CLK
clk[0] => pc[2].CLK
clk[0] => pc[3].CLK
clk[0] => pc[4].CLK
clk[0] => pc[5].CLK
clk[0] => pc[6].CLK
clk[0] => pc[7].CLK
clk[0] => pc[8].CLK
clk[0] => pc[9].CLK
clk[0] => pc[10].CLK
clk[0] => pc[11].CLK
clk[0] => pc[12].CLK
clk[0] => pc[13].CLK
clk[0] => pc[14].CLK
clk[0] => pc[15].CLK
clk[0] => pc[16].CLK
clk[0] => pc[17].CLK
clk[0] => pc[18].CLK
clk[0] => pc[19].CLK
clk[0] => pc[20].CLK
clk[0] => pc[21].CLK
clk[0] => pc[22].CLK
clk[0] => pc[23].CLK
clk[0] => pc[24].CLK
clk[0] => pc[25].CLK
clk[0] => pc[26].CLK
clk[0] => pc[27].CLK
clk[0] => pc[28].CLK
clk[0] => pc[29].CLK
clk[0] => pc[30].CLK
clk[0] => pc[31].CLK
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc.OUTPUTSELECT
we[0] => pc[0].ENA
we[0] => pc[1].ENA
W[0] => pc[0].DATAIN
W[1] => pc[1].DATAIN
W[2] => pc.DATAB
W[3] => pc.DATAB
W[4] => pc.DATAB
W[5] => pc.DATAB
W[6] => pc.DATAB
W[7] => pc.DATAB
W[8] => pc.DATAB
W[9] => pc.DATAB
W[10] => pc.DATAB
W[11] => pc.DATAB
W[12] => pc.DATAB
W[13] => pc.DATAB
W[14] => pc.DATAB
W[15] => pc.DATAB
W[16] => pc.DATAB
W[17] => pc.DATAB
W[18] => pc.DATAB
W[19] => pc.DATAB
W[20] => pc.DATAB
W[21] => pc.DATAB
W[22] => pc.DATAB
W[23] => pc.DATAB
W[24] => pc.DATAB
W[25] => pc.DATAB
W[26] => pc.DATAB
W[27] => pc.DATAB
W[28] => pc.DATAB
W[29] => pc.DATAB
W[30] => pc.DATAB
W[31] => pc.DATAB
addr[0] <= pc[0].DB_MAX_OUTPUT_PORT_TYPE
addr[1] <= pc[1].DB_MAX_OUTPUT_PORT_TYPE
addr[2] <= pc[2].DB_MAX_OUTPUT_PORT_TYPE
addr[3] <= pc[3].DB_MAX_OUTPUT_PORT_TYPE
addr[4] <= pc[4].DB_MAX_OUTPUT_PORT_TYPE
addr[5] <= pc[5].DB_MAX_OUTPUT_PORT_TYPE
addr[6] <= pc[6].DB_MAX_OUTPUT_PORT_TYPE
addr[7] <= pc[7].DB_MAX_OUTPUT_PORT_TYPE
addr[8] <= pc[8].DB_MAX_OUTPUT_PORT_TYPE
addr[9] <= pc[9].DB_MAX_OUTPUT_PORT_TYPE
addr[10] <= pc[10].DB_MAX_OUTPUT_PORT_TYPE
addr[11] <= pc[11].DB_MAX_OUTPUT_PORT_TYPE
addr[12] <= pc[12].DB_MAX_OUTPUT_PORT_TYPE
addr[13] <= pc[13].DB_MAX_OUTPUT_PORT_TYPE
addr[14] <= pc[14].DB_MAX_OUTPUT_PORT_TYPE
addr[15] <= pc[15].DB_MAX_OUTPUT_PORT_TYPE
addr[16] <= pc[16].DB_MAX_OUTPUT_PORT_TYPE
addr[17] <= pc[17].DB_MAX_OUTPUT_PORT_TYPE
addr[18] <= pc[18].DB_MAX_OUTPUT_PORT_TYPE
addr[19] <= pc[19].DB_MAX_OUTPUT_PORT_TYPE
addr[20] <= pc[20].DB_MAX_OUTPUT_PORT_TYPE
addr[21] <= pc[21].DB_MAX_OUTPUT_PORT_TYPE
addr[22] <= pc[22].DB_MAX_OUTPUT_PORT_TYPE
addr[23] <= pc[23].DB_MAX_OUTPUT_PORT_TYPE
addr[24] <= pc[24].DB_MAX_OUTPUT_PORT_TYPE
addr[25] <= pc[25].DB_MAX_OUTPUT_PORT_TYPE
addr[26] <= pc[26].DB_MAX_OUTPUT_PORT_TYPE
addr[27] <= pc[27].DB_MAX_OUTPUT_PORT_TYPE
addr[28] <= pc[28].DB_MAX_OUTPUT_PORT_TYPE
addr[29] <= pc[29].DB_MAX_OUTPUT_PORT_TYPE
addr[30] <= pc[30].DB_MAX_OUTPUT_PORT_TYPE
addr[31] <= pc[31].DB_MAX_OUTPUT_PORT_TYPE
|assignment2|rom:ROM
Ad[0] => mem.RADDR
Ad[1] => mem.RADDR1
Ad[2] => mem.RADDR2
Ad[3] => mem.RADDR3
Ad[4] => mem.RADDR4
Ad[5] => mem.RADDR5
Ad[6] => mem.RADDR6
Ad[7] => mem.RADDR7
Ad[8] => mem.RADDR8
Ad[9] => mem.RADDR9
Dout[0] <= mem.DATAOUT
Dout[1] <= mem.DATAOUT1
Dout[2] <= mem.DATAOUT2
Dout[3] <= mem.DATAOUT3
Dout[4] <= mem.DATAOUT4
Dout[5] <= mem.DATAOUT5
Dout[6] <= mem.DATAOUT6
Dout[7] <= mem.DATAOUT7
Dout[8] <= mem.DATAOUT8
Dout[9] <= mem.DATAOUT9
Dout[10] <= mem.DATAOUT10
Dout[11] <= mem.DATAOUT11
Dout[12] <= mem.DATAOUT12
Dout[13] <= mem.DATAOUT13
Dout[14] <= mem.DATAOUT14
Dout[15] <= mem.DATAOUT15
Dout[16] <= mem.DATAOUT16
Dout[17] <= mem.DATAOUT17
Dout[18] <= mem.DATAOUT18
Dout[19] <= mem.DATAOUT19
Dout[20] <= mem.DATAOUT20
Dout[21] <= mem.DATAOUT21
Dout[22] <= mem.DATAOUT22
Dout[23] <= mem.DATAOUT23
Dout[24] <= mem.DATAOUT24
Dout[25] <= mem.DATAOUT25
Dout[26] <= mem.DATAOUT26
Dout[27] <= mem.DATAOUT27
Dout[28] <= mem.DATAOUT28
Dout[29] <= mem.DATAOUT29
Dout[30] <= mem.DATAOUT30
Dout[31] <= mem.DATAOUT31
|assignment2|instruction_classifier:INSTRUCTION_CLASSIFIER
op[0] => Equal0.IN5
op[0] => Equal1.IN0
op[1] => Equal0.IN4
op[1] => Equal1.IN5
op[1] => Equal2.IN0
op[2] => Equal0.IN3
op[2] => Equal1.IN4
op[2] => Equal2.IN4
op[2] => Equal3.IN0
op[3] => Equal0.IN2
op[3] => Equal1.IN3
op[3] => Equal2.IN3
op[3] => Equal3.IN3
op[3] => Equal4.IN0
op[4] => Equal0.IN1
op[4] => Equal1.IN2
op[4] => Equal2.IN2
op[4] => Equal3.IN2
op[4] => Equal4.IN2
op[4] => Equal5.IN0
op[5] => M[0].DATAIN
op[5] => Equal0.IN0
op[5] => Equal1.IN1
op[5] => Equal2.IN1
op[5] => Equal3.IN1
op[5] => Equal4.IN1
op[5] => Equal5.IN1
R[0] <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
B1[0] <= Equal1.DB_MAX_OUTPUT_PORT_TYPE
J[0] <= Equal2.DB_MAX_OUTPUT_PORT_TYPE
B2[0] <= Equal3.DB_MAX_OUTPUT_PORT_TYPE
I[0] <= Equal4.DB_MAX_OUTPUT_PORT_TYPE
F[0] <= Equal5.DB_MAX_OUTPUT_PORT_TYPE
M[0] <= op[5].DB_MAX_OUTPUT_PORT_TYPE
|assignment2|instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER
op[0] => Equal0.IN2
op[0] => Equal1.IN0
op[1] => Equal0.IN1
op[1] => Equal1.IN2
op[1] => Equal2.IN0
op[2] => en_alu.DATAIN
op[2] => Equal0.IN0
op[2] => Equal1.IN1
op[2] => Equal2.IN1
en_shifter <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
en_jmp <= Equal1.DB_MAX_OUTPUT_PORT_TYPE
en_mul <= Equal2.DB_MAX_OUTPUT_PORT_TYPE
en_alu <= op[2].DB_MAX_OUTPUT_PORT_TYPE
|assignment2|register_file:REGS
clk[0] => regs.we_a.CLK
clk[0] => regs.waddr_a[4].CLK
clk[0] => regs.waddr_a[3].CLK
clk[0] => regs.waddr_a[2].CLK
clk[0] => regs.waddr_a[1].CLK
clk[0] => regs.waddr_a[0].CLK
clk[0] => regs.data_a[31].CLK
clk[0] => regs.data_a[30].CLK
clk[0] => regs.data_a[29].CLK
clk[0] => regs.data_a[28].CLK
clk[0] => regs.data_a[27].CLK
clk[0] => regs.data_a[26].CLK
clk[0] => regs.data_a[25].CLK
clk[0] => regs.data_a[24].CLK
clk[0] => regs.data_a[23].CLK
clk[0] => regs.data_a[22].CLK
clk[0] => regs.data_a[21].CLK
clk[0] => regs.data_a[20].CLK
clk[0] => regs.data_a[19].CLK
clk[0] => regs.data_a[18].CLK
clk[0] => regs.data_a[17].CLK
clk[0] => regs.data_a[16].CLK
clk[0] => regs.data_a[15].CLK
clk[0] => regs.data_a[14].CLK
clk[0] => regs.data_a[13].CLK
clk[0] => regs.data_a[12].CLK
clk[0] => regs.data_a[11].CLK
clk[0] => regs.data_a[10].CLK
clk[0] => regs.data_a[9].CLK
clk[0] => regs.data_a[8].CLK
clk[0] => regs.data_a[7].CLK
clk[0] => regs.data_a[6].CLK
clk[0] => regs.data_a[5].CLK
clk[0] => regs.data_a[4].CLK
clk[0] => regs.data_a[3].CLK
clk[0] => regs.data_a[2].CLK
clk[0] => regs.data_a[1].CLK
clk[0] => regs.data_a[0].CLK
clk[0] => regs.CLK0
we[0] => always0.IN1
WA[0] => regs.waddr_a[0].DATAIN
WA[0] => Equal0.IN31
WA[0] => regs.WADDR
WA[1] => regs.waddr_a[1].DATAIN
WA[1] => Equal0.IN30
WA[1] => regs.WADDR1
WA[2] => regs.waddr_a[2].DATAIN
WA[2] => Equal0.IN29
WA[2] => regs.WADDR2
WA[3] => regs.waddr_a[3].DATAIN
WA[3] => Equal0.IN28
WA[3] => regs.WADDR3
WA[4] => regs.waddr_a[4].DATAIN
WA[4] => Equal0.IN27
WA[4] => regs.WADDR4
WD[0] => regs.data_a[0].DATAIN
WD[0] => regs.DATAIN
WD[1] => regs.data_a[1].DATAIN
WD[1] => regs.DATAIN1
WD[2] => regs.data_a[2].DATAIN
WD[2] => regs.DATAIN2
WD[3] => regs.data_a[3].DATAIN
WD[3] => regs.DATAIN3
WD[4] => regs.data_a[4].DATAIN
WD[4] => regs.DATAIN4
WD[5] => regs.data_a[5].DATAIN
WD[5] => regs.DATAIN5
WD[6] => regs.data_a[6].DATAIN
WD[6] => regs.DATAIN6
WD[7] => regs.data_a[7].DATAIN
WD[7] => regs.DATAIN7
WD[8] => regs.data_a[8].DATAIN
WD[8] => regs.DATAIN8
WD[9] => regs.data_a[9].DATAIN
WD[9] => regs.DATAIN9
WD[10] => regs.data_a[10].DATAIN
WD[10] => regs.DATAIN10
WD[11] => regs.data_a[11].DATAIN
WD[11] => regs.DATAIN11
WD[12] => regs.data_a[12].DATAIN
WD[12] => regs.DATAIN12
WD[13] => regs.data_a[13].DATAIN
WD[13] => regs.DATAIN13
WD[14] => regs.data_a[14].DATAIN
WD[14] => regs.DATAIN14
WD[15] => regs.data_a[15].DATAIN
WD[15] => regs.DATAIN15
WD[16] => regs.data_a[16].DATAIN
WD[16] => regs.DATAIN16
WD[17] => regs.data_a[17].DATAIN
WD[17] => regs.DATAIN17
WD[18] => regs.data_a[18].DATAIN
WD[18] => regs.DATAIN18
WD[19] => regs.data_a[19].DATAIN
WD[19] => regs.DATAIN19
WD[20] => regs.data_a[20].DATAIN
WD[20] => regs.DATAIN20
WD[21] => regs.data_a[21].DATAIN
WD[21] => regs.DATAIN21
WD[22] => regs.data_a[22].DATAIN
WD[22] => regs.DATAIN22
WD[23] => regs.data_a[23].DATAIN
WD[23] => regs.DATAIN23
WD[24] => regs.data_a[24].DATAIN
WD[24] => regs.DATAIN24
WD[25] => regs.data_a[25].DATAIN
WD[25] => regs.DATAIN25
WD[26] => regs.data_a[26].DATAIN
WD[26] => regs.DATAIN26
WD[27] => regs.data_a[27].DATAIN
WD[27] => regs.DATAIN27
WD[28] => regs.data_a[28].DATAIN
WD[28] => regs.DATAIN28
WD[29] => regs.data_a[29].DATAIN
WD[29] => regs.DATAIN29
WD[30] => regs.data_a[30].DATAIN
WD[30] => regs.DATAIN30
WD[31] => regs.data_a[31].DATAIN
WD[31] => regs.DATAIN31
RA1[0] => regs.RADDR
RA1[1] => regs.RADDR1
RA1[2] => regs.RADDR2
RA1[3] => regs.RADDR3
RA1[4] => regs.RADDR4
RD1[0] <= regs.DATAOUT
RD1[1] <= regs.DATAOUT1
RD1[2] <= regs.DATAOUT2
RD1[3] <= regs.DATAOUT3
RD1[4] <= regs.DATAOUT4
RD1[5] <= regs.DATAOUT5
RD1[6] <= regs.DATAOUT6
RD1[7] <= regs.DATAOUT7
RD1[8] <= regs.DATAOUT8
RD1[9] <= regs.DATAOUT9
RD1[10] <= regs.DATAOUT10
RD1[11] <= regs.DATAOUT11
RD1[12] <= regs.DATAOUT12
RD1[13] <= regs.DATAOUT13
RD1[14] <= regs.DATAOUT14
RD1[15] <= regs.DATAOUT15
RD1[16] <= regs.DATAOUT16
RD1[17] <= regs.DATAOUT17
RD1[18] <= regs.DATAOUT18
RD1[19] <= regs.DATAOUT19
RD1[20] <= regs.DATAOUT20
RD1[21] <= regs.DATAOUT21
RD1[22] <= regs.DATAOUT22
RD1[23] <= regs.DATAOUT23
RD1[24] <= regs.DATAOUT24
RD1[25] <= regs.DATAOUT25
RD1[26] <= regs.DATAOUT26
RD1[27] <= regs.DATAOUT27
RD1[28] <= regs.DATAOUT28
RD1[29] <= regs.DATAOUT29
RD1[30] <= regs.DATAOUT30
RD1[31] <= regs.DATAOUT31
RA2[0] => regs.PORTBRADDR
RA2[1] => regs.PORTBRADDR1
RA2[2] => regs.PORTBRADDR2
RA2[3] => regs.PORTBRADDR3
RA2[4] => regs.PORTBRADDR4
RD2[0] <= regs.PORTBDATAOUT
RD2[1] <= regs.PORTBDATAOUT1
RD2[2] <= regs.PORTBDATAOUT2
RD2[3] <= regs.PORTBDATAOUT3
RD2[4] <= regs.PORTBDATAOUT4
RD2[5] <= regs.PORTBDATAOUT5
RD2[6] <= regs.PORTBDATAOUT6
RD2[7] <= regs.PORTBDATAOUT7
RD2[8] <= regs.PORTBDATAOUT8
RD2[9] <= regs.PORTBDATAOUT9
RD2[10] <= regs.PORTBDATAOUT10
RD2[11] <= regs.PORTBDATAOUT11
RD2[12] <= regs.PORTBDATAOUT12
RD2[13] <= regs.PORTBDATAOUT13
RD2[14] <= regs.PORTBDATAOUT14
RD2[15] <= regs.PORTBDATAOUT15
RD2[16] <= regs.PORTBDATAOUT16
RD2[17] <= regs.PORTBDATAOUT17
RD2[18] <= regs.PORTBDATAOUT18
RD2[19] <= regs.PORTBDATAOUT19
RD2[20] <= regs.PORTBDATAOUT20
RD2[21] <= regs.PORTBDATAOUT21
RD2[22] <= regs.PORTBDATAOUT22
RD2[23] <= regs.PORTBDATAOUT23
RD2[24] <= regs.PORTBDATAOUT24
RD2[25] <= regs.PORTBDATAOUT25
RD2[26] <= regs.PORTBDATAOUT26
RD2[27] <= regs.PORTBDATAOUT27
RD2[28] <= regs.PORTBDATAOUT28
RD2[29] <= regs.PORTBDATAOUT29
RD2[30] <= regs.PORTBDATAOUT30
RD2[31] <= regs.PORTBDATAOUT31
|assignment2|alu:ALU
op[0] => op[0].IN1
op[1] => op[1].IN1
op[2] => Mux0.IN3
op[2] => Mux1.IN3
op[2] => Mux2.IN3
op[2] => Mux3.IN3
op[2] => Mux4.IN3
op[2] => Mux5.IN3
op[2] => Mux6.IN3
op[2] => Mux7.IN3
op[2] => Mux8.IN3
op[2] => Mux9.IN3
op[2] => Mux10.IN3
op[2] => Mux11.IN3
op[2] => Mux12.IN3
op[2] => Mux13.IN3
op[2] => Mux14.IN3
op[2] => Mux15.IN3
op[2] => Mux16.IN3
op[2] => Mux17.IN3
op[2] => Mux18.IN3
op[2] => Mux19.IN3
op[2] => Mux20.IN3
op[2] => Mux21.IN3
op[2] => Mux22.IN3
op[2] => Mux23.IN3
op[2] => Mux24.IN3
op[2] => Mux25.IN3
op[2] => Mux26.IN3
op[2] => Mux27.IN3
op[2] => Mux28.IN3
op[2] => Mux29.IN3
op[2] => Mux30.IN3
op[2] => Mux31.IN9
op[3] => Mux0.IN2
op[3] => Mux1.IN2
op[3] => Mux2.IN2
op[3] => Mux3.IN2
op[3] => Mux4.IN2
op[3] => Mux5.IN2
op[3] => Mux6.IN2
op[3] => Mux7.IN2
op[3] => Mux8.IN2
op[3] => Mux9.IN2
op[3] => Mux10.IN2
op[3] => Mux11.IN2
op[3] => Mux12.IN2
op[3] => Mux13.IN2
op[3] => Mux14.IN2
op[3] => Mux15.IN2
op[3] => Mux16.IN2
op[3] => Mux17.IN2
op[3] => Mux18.IN2
op[3] => Mux19.IN2
op[3] => Mux20.IN2
op[3] => Mux21.IN2
op[3] => Mux22.IN2
op[3] => Mux23.IN2
op[3] => Mux24.IN2
op[3] => Mux25.IN2
op[3] => Mux26.IN2
op[3] => Mux27.IN2
op[3] => Mux28.IN2
op[3] => Mux29.IN2
op[3] => Mux30.IN2
op[3] => Mux31.IN8
A[0] => A[0].IN2
A[1] => A[1].IN2
A[2] => A[2].IN2
A[3] => A[3].IN2
A[4] => A[4].IN2
A[5] => A[5].IN2
A[6] => A[6].IN2
A[7] => A[7].IN2
A[8] => A[8].IN2
A[9] => A[9].IN2
A[10] => A[10].IN2
A[11] => A[11].IN2
A[12] => A[12].IN2
A[13] => A[13].IN2
A[14] => A[14].IN2
A[15] => A[15].IN2
A[16] => A[16].IN2
A[17] => A[17].IN2
A[18] => A[18].IN2
A[19] => A[19].IN2
A[20] => A[20].IN2
A[21] => A[21].IN2
A[22] => A[22].IN2
A[23] => A[23].IN2
A[24] => A[24].IN2
A[25] => A[25].IN2
A[26] => A[26].IN2
A[27] => A[27].IN2
A[28] => A[28].IN2
A[29] => A[29].IN2
A[30] => A[30].IN2
A[31] => A[31].IN2
B[0] => B[0].IN2
B[1] => B[1].IN2
B[2] => B[2].IN2
B[3] => B[3].IN2
B[4] => B[4].IN2
B[5] => B[5].IN2
B[6] => B[6].IN2
B[7] => B[7].IN2
B[8] => B[8].IN2
B[9] => B[9].IN2
B[10] => B[10].IN2
B[11] => B[11].IN2
B[12] => B[12].IN2
B[13] => B[13].IN2
B[14] => B[14].IN2
B[15] => B[15].IN2
B[16] => B[16].IN2
B[17] => B[17].IN2
B[18] => B[18].IN2
B[19] => B[19].IN2
B[20] => B[20].IN2
B[21] => B[21].IN2
B[22] => B[22].IN2
B[23] => B[23].IN2
B[24] => B[24].IN2
B[25] => B[25].IN2
B[26] => B[26].IN2
B[27] => B[27].IN2
B[28] => B[28].IN2
B[29] => B[29].IN2
B[30] => B[30].IN2
B[31] => B[31].IN2
OUT_1[0] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[1] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[2] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[3] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[4] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[6] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[7] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[8] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[9] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[10] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[11] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[12] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[13] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[14] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[15] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[16] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[17] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[18] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[19] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[20] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[21] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[22] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[23] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[24] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[25] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[26] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[27] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[28] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[29] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
flags[0] <= asu:adder_unit.port4
flags[1] <= asu:adder_unit.port5
|assignment2|alu:ALU|asu:adder_unit
op[0] => operand[31].OUTPUTSELECT
op[0] => operand[30].OUTPUTSELECT
op[0] => operand[29].OUTPUTSELECT
op[0] => operand[28].OUTPUTSELECT
op[0] => operand[27].OUTPUTSELECT
op[0] => operand[26].OUTPUTSELECT
op[0] => operand[25].OUTPUTSELECT
op[0] => operand[24].OUTPUTSELECT
op[0] => operand[23].OUTPUTSELECT
op[0] => operand[22].OUTPUTSELECT
op[0] => operand[21].OUTPUTSELECT
op[0] => operand[20].OUTPUTSELECT
op[0] => operand[19].OUTPUTSELECT
op[0] => operand[18].OUTPUTSELECT
op[0] => operand[17].OUTPUTSELECT
op[0] => operand[16].OUTPUTSELECT
op[0] => operand[15].OUTPUTSELECT
op[0] => operand[14].OUTPUTSELECT
op[0] => operand[13].OUTPUTSELECT
op[0] => operand[12].OUTPUTSELECT
op[0] => operand[11].OUTPUTSELECT
op[0] => operand[10].OUTPUTSELECT
op[0] => operand[9].OUTPUTSELECT
op[0] => operand[8].OUTPUTSELECT
op[0] => operand[7].OUTPUTSELECT
op[0] => operand[6].OUTPUTSELECT
op[0] => operand[5].OUTPUTSELECT
op[0] => operand[4].OUTPUTSELECT
op[0] => operand[3].OUTPUTSELECT
op[0] => operand[2].OUTPUTSELECT
op[0] => operand[1].OUTPUTSELECT
op[0] => operand[0].OUTPUTSELECT
op[0] => _.DATAB
A[0] => _.DATAD
A[1] => _.DATAD
A[2] => _.DATAD
A[3] => _.DATAD
A[4] => _.DATAD
A[5] => _.DATAD
A[6] => _.DATAD
A[7] => _.DATAD
A[8] => _.DATAD
A[9] => _.DATAD
A[10] => _.DATAD
A[11] => _.DATAD
A[12] => _.DATAD
A[13] => _.DATAD
A[14] => _.DATAD
A[15] => _.DATAD
A[16] => _.DATAD
A[17] => _.DATAD
A[18] => _.DATAD
A[19] => _.DATAD
A[20] => _.DATAD
A[21] => _.DATAD
A[22] => _.DATAD
A[23] => _.DATAD
A[24] => _.DATAD
A[25] => _.DATAD
A[26] => _.DATAD
A[27] => _.DATAD
A[28] => _.DATAD
A[29] => _.DATAD
A[30] => _.DATAD
A[31] => OUT_CIN.IN1
A[31] => _.DATAD
B[0] => operand[0].DATAB
B[0] => operand[0].DATAA
B[1] => operand[1].DATAB
B[1] => operand[1].DATAA
B[2] => operand[2].DATAB
B[2] => operand[2].DATAA
B[3] => operand[3].DATAB
B[3] => operand[3].DATAA
B[4] => operand[4].DATAB
B[4] => operand[4].DATAA
B[5] => operand[5].DATAB
B[5] => operand[5].DATAA
B[6] => operand[6].DATAB
B[6] => operand[6].DATAA
B[7] => operand[7].DATAB
B[7] => operand[7].DATAA
B[8] => operand[8].DATAB
B[8] => operand[8].DATAA
B[9] => operand[9].DATAB
B[9] => operand[9].DATAA
B[10] => operand[10].DATAB
B[10] => operand[10].DATAA
B[11] => operand[11].DATAB
B[11] => operand[11].DATAA
B[12] => operand[12].DATAB
B[12] => operand[12].DATAA
B[13] => operand[13].DATAB
B[13] => operand[13].DATAA
B[14] => operand[14].DATAB
B[14] => operand[14].DATAA
B[15] => operand[15].DATAB
B[15] => operand[15].DATAA
B[16] => operand[16].DATAB
B[16] => operand[16].DATAA
B[17] => operand[17].DATAB
B[17] => operand[17].DATAA
B[18] => operand[18].DATAB
B[18] => operand[18].DATAA
B[19] => operand[19].DATAB
B[19] => operand[19].DATAA
B[20] => operand[20].DATAB
B[20] => operand[20].DATAA
B[21] => operand[21].DATAB
B[21] => operand[21].DATAA
B[22] => operand[22].DATAB
B[22] => operand[22].DATAA
B[23] => operand[23].DATAB
B[23] => operand[23].DATAA
B[24] => operand[24].DATAB
B[24] => operand[24].DATAA
B[25] => operand[25].DATAB
B[25] => operand[25].DATAA
B[26] => operand[26].DATAB
B[26] => operand[26].DATAA
B[27] => operand[27].DATAB
B[27] => operand[27].DATAA
B[28] => operand[28].DATAB
B[28] => operand[28].DATAA
B[29] => operand[29].DATAB
B[29] => operand[29].DATAA
B[30] => operand[30].DATAB
B[30] => operand[30].DATAA
B[31] => operand[31].DATAB
B[31] => operand[31].DATAA
OUT_1[0] <= _.SUM_OUT
OUT_1[1] <= _.SUM_OUT
OUT_1[2] <= _.SUM_OUT
OUT_1[3] <= _.SUM_OUT
OUT_1[4] <= _.SUM_OUT
OUT_1[5] <= _.SUM_OUT
OUT_1[6] <= _.SUM_OUT
OUT_1[7] <= _.SUM_OUT
OUT_1[8] <= _.SUM_OUT
OUT_1[9] <= _.SUM_OUT
OUT_1[10] <= _.SUM_OUT
OUT_1[11] <= _.SUM_OUT
OUT_1[12] <= _.SUM_OUT
OUT_1[13] <= _.SUM_OUT
OUT_1[14] <= _.SUM_OUT
OUT_1[15] <= _.SUM_OUT
OUT_1[16] <= _.SUM_OUT
OUT_1[17] <= _.SUM_OUT
OUT_1[18] <= _.SUM_OUT
OUT_1[19] <= _.SUM_OUT
OUT_1[20] <= _.SUM_OUT
OUT_1[21] <= _.SUM_OUT
OUT_1[22] <= _.SUM_OUT
OUT_1[23] <= _.SUM_OUT
OUT_1[24] <= _.SUM_OUT
OUT_1[25] <= _.SUM_OUT
OUT_1[26] <= _.SUM_OUT
OUT_1[27] <= _.SUM_OUT
OUT_1[28] <= _.SUM_OUT
OUT_1[29] <= _.SUM_OUT
OUT_1[30] <= _.SUM_OUT
OUT_1[31] <= _.SUM_OUT
COUT[0] <= _.SUM_OUT
OUT_CIN[0] <= OUT_CIN.DB_MAX_OUTPUT_PORT_TYPE
|assignment2|alu:ALU|lu:logic_unit
op[0] => Mux0.IN5
op[0] => Mux1.IN5
op[0] => Mux2.IN5
op[0] => Mux3.IN5
op[0] => Mux4.IN5
op[0] => Mux5.IN5
op[0] => Mux6.IN5
op[0] => Mux7.IN5
op[0] => Mux8.IN5
op[0] => Mux9.IN5
op[0] => Mux10.IN5
op[0] => Mux11.IN5
op[0] => Mux12.IN5
op[0] => Mux13.IN5
op[0] => Mux14.IN5
op[0] => Mux15.IN5
op[0] => Mux16.IN5
op[0] => Mux17.IN5
op[0] => Mux18.IN5
op[0] => Mux19.IN5
op[0] => Mux20.IN5
op[0] => Mux21.IN5
op[0] => Mux22.IN5
op[0] => Mux23.IN5
op[0] => Mux24.IN5
op[0] => Mux25.IN5
op[0] => Mux26.IN5
op[0] => Mux27.IN5
op[0] => Mux28.IN5
op[0] => Mux29.IN5
op[0] => Mux30.IN5
op[0] => Mux31.IN5
op[1] => Mux0.IN4
op[1] => Mux1.IN4
op[1] => Mux2.IN4
op[1] => Mux3.IN4
op[1] => Mux4.IN4
op[1] => Mux5.IN4
op[1] => Mux6.IN4
op[1] => Mux7.IN4
op[1] => Mux8.IN4
op[1] => Mux9.IN4
op[1] => Mux10.IN4
op[1] => Mux11.IN4
op[1] => Mux12.IN4
op[1] => Mux13.IN4
op[1] => Mux14.IN4
op[1] => Mux15.IN4
op[1] => Mux16.IN4
op[1] => Mux17.IN4
op[1] => Mux18.IN4
op[1] => Mux19.IN4
op[1] => Mux20.IN4
op[1] => Mux21.IN4
op[1] => Mux22.IN4
op[1] => Mux23.IN4
op[1] => Mux24.IN4
op[1] => Mux25.IN4
op[1] => Mux26.IN4
op[1] => Mux27.IN4
op[1] => Mux28.IN4
op[1] => Mux29.IN4
op[1] => Mux30.IN4
op[1] => Mux31.IN4
A[0] => Y.IN0
A[0] => Y.IN0
A[0] => Y.IN0
A[1] => Y.IN0
A[1] => Y.IN0
A[1] => Y.IN0
A[2] => Y.IN0
A[2] => Y.IN0
A[2] => Y.IN0
A[3] => Y.IN0
A[3] => Y.IN0
A[3] => Y.IN0
A[4] => Y.IN0
A[4] => Y.IN0
A[4] => Y.IN0
A[5] => Y.IN0
A[5] => Y.IN0
A[5] => Y.IN0
A[6] => Y.IN0
A[6] => Y.IN0
A[6] => Y.IN0
A[7] => Y.IN0
A[7] => Y.IN0
A[7] => Y.IN0
A[8] => Y.IN0
A[8] => Y.IN0
A[8] => Y.IN0
A[9] => Y.IN0
A[9] => Y.IN0
A[9] => Y.IN0
A[10] => Y.IN0
A[10] => Y.IN0
A[10] => Y.IN0
A[11] => Y.IN0
A[11] => Y.IN0
A[11] => Y.IN0
A[12] => Y.IN0
A[12] => Y.IN0
A[12] => Y.IN0
A[13] => Y.IN0
A[13] => Y.IN0
A[13] => Y.IN0
A[14] => Y.IN0
A[14] => Y.IN0
A[14] => Y.IN0
A[15] => Y.IN0
A[15] => Y.IN0
A[15] => Y.IN0
A[16] => Y.IN0
A[16] => Y.IN0
A[16] => Y.IN0
A[17] => Y.IN0
A[17] => Y.IN0
A[17] => Y.IN0
A[18] => Y.IN0
A[18] => Y.IN0
A[18] => Y.IN0
A[19] => Y.IN0
A[19] => Y.IN0
A[19] => Y.IN0
A[20] => Y.IN0
A[20] => Y.IN0
A[20] => Y.IN0
A[21] => Y.IN0
A[21] => Y.IN0
A[21] => Y.IN0
A[22] => Y.IN0
A[22] => Y.IN0
A[22] => Y.IN0
A[23] => Y.IN0
A[23] => Y.IN0
A[23] => Y.IN0
A[24] => Y.IN0
A[24] => Y.IN0
A[24] => Y.IN0
A[25] => Y.IN0
A[25] => Y.IN0
A[25] => Y.IN0
A[26] => Y.IN0
A[26] => Y.IN0
A[26] => Y.IN0
A[27] => Y.IN0
A[27] => Y.IN0
A[27] => Y.IN0
A[28] => Y.IN0
A[28] => Y.IN0
A[28] => Y.IN0
A[29] => Y.IN0
A[29] => Y.IN0
A[29] => Y.IN0
A[30] => Y.IN0
A[30] => Y.IN0
A[30] => Y.IN0
A[31] => Y.IN0
A[31] => Y.IN0
A[31] => Y.IN0
B[0] => Y.IN1
B[0] => Y.IN1
B[0] => Y.IN1
B[1] => Y.IN1
B[1] => Y.IN1
B[1] => Y.IN1
B[2] => Y.IN1
B[2] => Y.IN1
B[2] => Y.IN1
B[3] => Y.IN1
B[3] => Y.IN1
B[3] => Y.IN1
B[4] => Y.IN1
B[4] => Y.IN1
B[4] => Y.IN1
B[5] => Y.IN1
B[5] => Y.IN1
B[5] => Y.IN1
B[6] => Y.IN1
B[6] => Y.IN1
B[6] => Y.IN1
B[7] => Y.IN1
B[7] => Y.IN1
B[7] => Y.IN1
B[8] => Y.IN1
B[8] => Y.IN1
B[8] => Y.IN1
B[9] => Y.IN1
B[9] => Y.IN1
B[9] => Y.IN1
B[10] => Y.IN1
B[10] => Y.IN1
B[10] => Y.IN1
B[11] => Y.IN1
B[11] => Y.IN1
B[11] => Y.IN1
B[12] => Y.IN1
B[12] => Y.IN1
B[12] => Y.IN1
B[13] => Y.IN1
B[13] => Y.IN1
B[13] => Y.IN1
B[14] => Y.IN1
B[14] => Y.IN1
B[14] => Y.IN1
B[15] => Y.IN1
B[15] => Y.IN1
B[15] => Y.IN1
B[16] => Y.IN1
B[16] => Y.IN1
B[16] => Y.IN1
B[17] => Y.IN1
B[17] => Y.IN1
B[17] => Y.IN1
B[18] => Y.IN1
B[18] => Y.IN1
B[18] => Y.IN1
B[19] => Y.IN1
B[19] => Y.IN1
B[19] => Y.IN1
B[20] => Y.IN1
B[20] => Y.IN1
B[20] => Y.IN1
B[21] => Y.IN1
B[21] => Y.IN1
B[21] => Y.IN1
B[22] => Y.IN1
B[22] => Y.IN1
B[22] => Y.IN1
B[23] => Y.IN1
B[23] => Y.IN1
B[23] => Y.IN1
B[24] => Y.IN1
B[24] => Y.IN1
B[24] => Y.IN1
B[25] => Y.IN1
B[25] => Y.IN1
B[25] => Y.IN1
B[26] => Y.IN1
B[26] => Y.IN1
B[26] => Y.IN1
B[27] => Y.IN1
B[27] => Y.IN1
B[27] => Y.IN1
B[28] => Y.IN1
B[28] => Y.IN1
B[28] => Y.IN1
B[29] => Y.IN1
B[29] => Y.IN1
B[29] => Y.IN1
B[30] => Y.IN1
B[30] => Y.IN1
B[30] => Y.IN1
B[31] => Y.IN1
B[31] => Y.IN1
B[31] => Y.IN1
Y[0] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE
Y[1] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE
Y[2] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE
Y[3] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE
Y[4] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE
Y[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE
Y[6] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE
Y[7] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE
Y[8] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE
Y[9] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE
Y[10] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE
Y[11] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE
Y[12] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE
Y[13] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE
Y[14] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE
Y[15] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE
Y[16] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE
Y[17] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE
Y[18] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE
Y[19] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE
Y[20] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE
Y[21] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
Y[22] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
Y[23] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
Y[24] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
Y[25] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
Y[26] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
Y[27] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
Y[28] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
Y[29] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
Y[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Y[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
|assignment2|shifter:SHIFTER
op[0] => Mux0.IN8
op[0] => Mux1.IN8
op[0] => Mux2.IN8
op[0] => Mux3.IN8
op[0] => Mux4.IN8
op[0] => Mux5.IN8
op[0] => Mux6.IN8
op[0] => Mux7.IN8
op[0] => Mux8.IN8
op[0] => Mux9.IN8
op[0] => Mux10.IN8
op[0] => Mux11.IN8
op[0] => Mux12.IN8
op[0] => Mux13.IN8
op[0] => Mux14.IN8
op[0] => Mux15.IN8
op[0] => Mux16.IN8
op[0] => Mux17.IN8
op[0] => Mux18.IN8
op[0] => Mux19.IN8
op[0] => Mux20.IN8
op[0] => Mux21.IN8
op[0] => Mux22.IN8
op[0] => Mux23.IN8
op[0] => Mux24.IN8
op[0] => Mux25.IN8
op[0] => Mux26.IN8
op[0] => Mux27.IN8
op[0] => Mux28.IN8
op[0] => Mux29.IN8
op[0] => Mux30.IN8
op[0] => Mux31.IN8
op[1] => Mux0.IN7
op[1] => Mux1.IN7
op[1] => Mux2.IN7
op[1] => Mux3.IN7
op[1] => Mux4.IN7
op[1] => Mux5.IN7
op[1] => Mux6.IN7
op[1] => Mux7.IN7
op[1] => Mux8.IN7
op[1] => Mux9.IN7
op[1] => Mux10.IN7
op[1] => Mux11.IN7
op[1] => Mux12.IN7
op[1] => Mux13.IN7
op[1] => Mux14.IN7
op[1] => Mux15.IN7
op[1] => Mux16.IN7
op[1] => Mux17.IN7
op[1] => Mux18.IN7
op[1] => Mux19.IN7
op[1] => Mux20.IN7
op[1] => Mux21.IN7
op[1] => Mux22.IN7
op[1] => Mux23.IN7
op[1] => Mux24.IN7
op[1] => Mux25.IN7
op[1] => Mux26.IN7
op[1] => Mux27.IN7
op[1] => Mux28.IN7
op[1] => Mux29.IN7
op[1] => Mux30.IN7
op[1] => Mux31.IN7
op[2] => Mux0.IN6
op[2] => Mux1.IN6
op[2] => Mux2.IN6
op[2] => Mux3.IN6
op[2] => Mux4.IN6
op[2] => Mux5.IN6
op[2] => Mux6.IN6
op[2] => Mux7.IN6
op[2] => Mux8.IN6
op[2] => Mux9.IN6
op[2] => Mux10.IN6
op[2] => Mux11.IN6
op[2] => Mux12.IN6
op[2] => Mux13.IN6
op[2] => Mux14.IN6
op[2] => Mux15.IN6
op[2] => Mux16.IN6
op[2] => Mux17.IN6
op[2] => Mux18.IN6
op[2] => Mux19.IN6
op[2] => Mux20.IN6
op[2] => Mux21.IN6
op[2] => Mux22.IN6
op[2] => Mux23.IN6
op[2] => Mux24.IN6
op[2] => Mux25.IN6
op[2] => Mux26.IN6
op[2] => Mux27.IN6
op[2] => Mux28.IN6
op[2] => Mux29.IN6
op[2] => Mux30.IN6
op[2] => Mux31.IN6
A[0] => ShiftLeft0.IN32
A[0] => ShiftRight0.IN32
A[0] => ShiftRight1.IN32
A[0] => ShiftLeft1.IN32
A[0] => ShiftRight2.IN32
A[0] => ShiftRight3.IN32
A[0] => Mux31.IN9
A[0] => Mux31.IN10
A[1] => ShiftLeft0.IN31
A[1] => ShiftRight0.IN31
A[1] => ShiftRight1.IN31
A[1] => ShiftLeft1.IN31
A[1] => ShiftRight2.IN31
A[1] => ShiftRight3.IN31
A[1] => Mux30.IN9
A[1] => Mux30.IN10
A[2] => ShiftLeft0.IN30
A[2] => ShiftRight0.IN30
A[2] => ShiftRight1.IN30
A[2] => ShiftLeft1.IN30
A[2] => ShiftRight2.IN30
A[2] => ShiftRight3.IN30
A[2] => Mux29.IN9
A[2] => Mux29.IN10
A[3] => ShiftLeft0.IN29
A[3] => ShiftRight0.IN29
A[3] => ShiftRight1.IN29
A[3] => ShiftLeft1.IN29
A[3] => ShiftRight2.IN29
A[3] => ShiftRight3.IN29
A[3] => Mux28.IN9
A[3] => Mux28.IN10
A[4] => ShiftLeft0.IN28
A[4] => ShiftRight0.IN28
A[4] => ShiftRight1.IN28
A[4] => ShiftLeft1.IN28
A[4] => ShiftRight2.IN28
A[4] => ShiftRight3.IN28
A[4] => Mux27.IN9
A[4] => Mux27.IN10
A[5] => ShiftLeft0.IN27
A[5] => ShiftRight0.IN27
A[5] => ShiftRight1.IN27
A[5] => ShiftLeft1.IN27
A[5] => ShiftRight2.IN27
A[5] => ShiftRight3.IN27
A[5] => Mux26.IN9
A[5] => Mux26.IN10
A[6] => ShiftLeft0.IN26
A[6] => ShiftRight0.IN26
A[6] => ShiftRight1.IN26
A[6] => ShiftLeft1.IN26
A[6] => ShiftRight2.IN26
A[6] => ShiftRight3.IN26
A[6] => Mux25.IN9
A[6] => Mux25.IN10
A[7] => ShiftLeft0.IN25
A[7] => ShiftRight0.IN25
A[7] => ShiftRight1.IN25
A[7] => ShiftLeft1.IN25
A[7] => ShiftRight2.IN25
A[7] => ShiftRight3.IN25
A[7] => Mux24.IN9
A[7] => Mux24.IN10
A[8] => ShiftLeft0.IN24
A[8] => ShiftRight0.IN24
A[8] => ShiftRight1.IN24
A[8] => ShiftLeft1.IN24
A[8] => ShiftRight2.IN24
A[8] => ShiftRight3.IN24
A[8] => Mux23.IN9
A[8] => Mux23.IN10
A[9] => ShiftLeft0.IN23
A[9] => ShiftRight0.IN23
A[9] => ShiftRight1.IN23
A[9] => ShiftLeft1.IN23
A[9] => ShiftRight2.IN23
A[9] => ShiftRight3.IN23
A[9] => Mux22.IN9
A[9] => Mux22.IN10
A[10] => ShiftLeft0.IN22
A[10] => ShiftRight0.IN22
A[10] => ShiftRight1.IN22
A[10] => ShiftLeft1.IN22
A[10] => ShiftRight2.IN22
A[10] => ShiftRight3.IN22
A[10] => Mux21.IN9
A[10] => Mux21.IN10
A[11] => ShiftLeft0.IN21
A[11] => ShiftRight0.IN21
A[11] => ShiftRight1.IN21
A[11] => ShiftLeft1.IN21
A[11] => ShiftRight2.IN21
A[11] => ShiftRight3.IN21
A[11] => Mux20.IN9
A[11] => Mux20.IN10
A[12] => ShiftLeft0.IN20
A[12] => ShiftRight0.IN20
A[12] => ShiftRight1.IN20
A[12] => ShiftLeft1.IN20
A[12] => ShiftRight2.IN20
A[12] => ShiftRight3.IN20
A[12] => Mux19.IN9
A[12] => Mux19.IN10
A[13] => ShiftLeft0.IN19
A[13] => ShiftRight0.IN19
A[13] => ShiftRight1.IN19
A[13] => ShiftLeft1.IN19
A[13] => ShiftRight2.IN19
A[13] => ShiftRight3.IN19
A[13] => Mux18.IN9
A[13] => Mux18.IN10
A[14] => ShiftLeft0.IN18
A[14] => ShiftRight0.IN18
A[14] => ShiftRight1.IN18
A[14] => ShiftLeft1.IN18
A[14] => ShiftRight2.IN18
A[14] => ShiftRight3.IN18
A[14] => Mux17.IN9
A[14] => Mux17.IN10
A[15] => ShiftLeft0.IN17
A[15] => ShiftRight0.IN17
A[15] => ShiftRight1.IN17
A[15] => ShiftLeft1.IN17
A[15] => ShiftRight2.IN17
A[15] => ShiftRight3.IN17
A[15] => Mux16.IN9
A[15] => Mux16.IN10
A[16] => ShiftLeft0.IN16
A[16] => ShiftRight0.IN16
A[16] => ShiftRight1.IN16
A[16] => ShiftLeft1.IN16
A[16] => ShiftRight2.IN16
A[16] => ShiftRight3.IN16
A[16] => Mux15.IN9
A[16] => Mux15.IN10
A[17] => ShiftLeft0.IN15
A[17] => ShiftRight0.IN15
A[17] => ShiftRight1.IN15
A[17] => ShiftLeft1.IN15
A[17] => ShiftRight2.IN15
A[17] => ShiftRight3.IN15
A[17] => Mux14.IN9
A[17] => Mux14.IN10
A[18] => ShiftLeft0.IN14
A[18] => ShiftRight0.IN14
A[18] => ShiftRight1.IN14
A[18] => ShiftLeft1.IN14
A[18] => ShiftRight2.IN14
A[18] => ShiftRight3.IN14
A[18] => Mux13.IN9
A[18] => Mux13.IN10
A[19] => ShiftLeft0.IN13
A[19] => ShiftRight0.IN13
A[19] => ShiftRight1.IN13
A[19] => ShiftLeft1.IN13
A[19] => ShiftRight2.IN13
A[19] => ShiftRight3.IN13
A[19] => Mux12.IN9
A[19] => Mux12.IN10
A[20] => ShiftLeft0.IN12
A[20] => ShiftRight0.IN12
A[20] => ShiftRight1.IN12
A[20] => ShiftLeft1.IN12
A[20] => ShiftRight2.IN12
A[20] => ShiftRight3.IN12
A[20] => Mux11.IN9
A[20] => Mux11.IN10
A[21] => ShiftLeft0.IN11
A[21] => ShiftRight0.IN11
A[21] => ShiftRight1.IN11
A[21] => ShiftLeft1.IN11
A[21] => ShiftRight2.IN11
A[21] => ShiftRight3.IN11
A[21] => Mux10.IN9
A[21] => Mux10.IN10
A[22] => ShiftLeft0.IN10
A[22] => ShiftRight0.IN10
A[22] => ShiftRight1.IN10
A[22] => ShiftLeft1.IN10
A[22] => ShiftRight2.IN10
A[22] => ShiftRight3.IN10
A[22] => Mux9.IN9
A[22] => Mux9.IN10
A[23] => ShiftLeft0.IN9
A[23] => ShiftRight0.IN9
A[23] => ShiftRight1.IN9
A[23] => ShiftLeft1.IN9
A[23] => ShiftRight2.IN9
A[23] => ShiftRight3.IN9
A[23] => Mux8.IN9
A[23] => Mux8.IN10
A[24] => ShiftLeft0.IN8
A[24] => ShiftRight0.IN8
A[24] => ShiftRight1.IN8
A[24] => ShiftLeft1.IN8
A[24] => ShiftRight2.IN8
A[24] => ShiftRight3.IN8
A[24] => Mux7.IN9
A[24] => Mux7.IN10
A[25] => ShiftLeft0.IN7
A[25] => ShiftRight0.IN7
A[25] => ShiftRight1.IN7
A[25] => ShiftLeft1.IN7
A[25] => ShiftRight2.IN7
A[25] => ShiftRight3.IN7
A[25] => Mux6.IN9
A[25] => Mux6.IN10
A[26] => ShiftLeft0.IN6
A[26] => ShiftRight0.IN6
A[26] => ShiftRight1.IN6
A[26] => ShiftLeft1.IN6
A[26] => ShiftRight2.IN6
A[26] => ShiftRight3.IN6
A[26] => Mux5.IN9
A[26] => Mux5.IN10
A[27] => ShiftLeft0.IN5
A[27] => ShiftRight0.IN5
A[27] => ShiftRight1.IN5
A[27] => ShiftLeft1.IN5
A[27] => ShiftRight2.IN5
A[27] => ShiftRight3.IN5
A[27] => Mux4.IN9
A[27] => Mux4.IN10
A[28] => ShiftLeft0.IN4
A[28] => ShiftRight0.IN4
A[28] => ShiftRight1.IN4
A[28] => ShiftLeft1.IN4
A[28] => ShiftRight2.IN4
A[28] => ShiftRight3.IN4
A[28] => Mux3.IN9
A[28] => Mux3.IN10
A[29] => ShiftLeft0.IN3
A[29] => ShiftRight0.IN3
A[29] => ShiftRight1.IN3
A[29] => ShiftLeft1.IN3
A[29] => ShiftRight2.IN3
A[29] => ShiftRight3.IN3
A[29] => Mux2.IN9
A[29] => Mux2.IN10
A[30] => ShiftLeft0.IN2
A[30] => ShiftRight0.IN2
A[30] => ShiftRight1.IN2
A[30] => ShiftLeft1.IN2
A[30] => ShiftRight2.IN2
A[30] => ShiftRight3.IN2
A[30] => Mux1.IN9
A[30] => Mux1.IN10
A[31] => ShiftLeft0.IN1
A[31] => ShiftRight0.IN1
A[31] => ShiftRight1.IN0
A[31] => ShiftRight1.IN1
A[31] => ShiftLeft1.IN1
A[31] => ShiftRight2.IN1
A[31] => ShiftRight3.IN0
A[31] => ShiftRight3.IN1
A[31] => Mux0.IN9
A[31] => Mux0.IN10
B[0] => ShiftLeft1.IN64
B[0] => ShiftRight2.IN64
B[0] => ShiftRight3.IN64
B[1] => ShiftLeft1.IN63
B[1] => ShiftRight2.IN63
B[1] => ShiftRight3.IN63
B[2] => ShiftLeft1.IN62
B[2] => ShiftRight2.IN62
B[2] => ShiftRight3.IN62
B[3] => ShiftLeft1.IN61
B[3] => ShiftRight2.IN61
B[3] => ShiftRight3.IN61
B[4] => ShiftLeft1.IN60
B[4] => ShiftRight2.IN60
B[4] => ShiftRight3.IN60
B[5] => ShiftLeft1.IN59
B[5] => ShiftRight2.IN59
B[5] => ShiftRight3.IN59
B[6] => ShiftLeft1.IN58
B[6] => ShiftRight2.IN58
B[6] => ShiftRight3.IN58
B[7] => ShiftLeft1.IN57
B[7] => ShiftRight2.IN57
B[7] => ShiftRight3.IN57
B[8] => ShiftLeft1.IN56
B[8] => ShiftRight2.IN56
B[8] => ShiftRight3.IN56
B[9] => ShiftLeft1.IN55
B[9] => ShiftRight2.IN55
B[9] => ShiftRight3.IN55
B[10] => ShiftLeft1.IN54
B[10] => ShiftRight2.IN54
B[10] => ShiftRight3.IN54
B[11] => ShiftLeft1.IN53
B[11] => ShiftRight2.IN53
B[11] => ShiftRight3.IN53
B[12] => ShiftLeft1.IN52
B[12] => ShiftRight2.IN52
B[12] => ShiftRight3.IN52
B[13] => ShiftLeft1.IN51
B[13] => ShiftRight2.IN51
B[13] => ShiftRight3.IN51
B[14] => ShiftLeft1.IN50
B[14] => ShiftRight2.IN50
B[14] => ShiftRight3.IN50
B[15] => ShiftLeft1.IN49
B[15] => ShiftRight2.IN49
B[15] => ShiftRight3.IN49
B[16] => ShiftLeft1.IN48
B[16] => ShiftRight2.IN48
B[16] => ShiftRight3.IN48
B[17] => ShiftLeft1.IN47
B[17] => ShiftRight2.IN47
B[17] => ShiftRight3.IN47
B[18] => ShiftLeft1.IN46
B[18] => ShiftRight2.IN46
B[18] => ShiftRight3.IN46
B[19] => ShiftLeft1.IN45
B[19] => ShiftRight2.IN45
B[19] => ShiftRight3.IN45
B[20] => ShiftLeft1.IN44
B[20] => ShiftRight2.IN44
B[20] => ShiftRight3.IN44
B[21] => ShiftLeft1.IN43
B[21] => ShiftRight2.IN43
B[21] => ShiftRight3.IN43
B[22] => ShiftLeft1.IN42
B[22] => ShiftRight2.IN42
B[22] => ShiftRight3.IN42
B[23] => ShiftLeft1.IN41
B[23] => ShiftRight2.IN41
B[23] => ShiftRight3.IN41
B[24] => ShiftLeft1.IN40
B[24] => ShiftRight2.IN40
B[24] => ShiftRight3.IN40
B[25] => ShiftLeft1.IN39
B[25] => ShiftRight2.IN39
B[25] => ShiftRight3.IN39
B[26] => ShiftLeft1.IN38
B[26] => ShiftRight2.IN38
B[26] => ShiftRight3.IN38
B[27] => ShiftLeft1.IN37
B[27] => ShiftRight2.IN37
B[27] => ShiftRight3.IN37
B[28] => ShiftLeft1.IN36
B[28] => ShiftRight2.IN36
B[28] => ShiftRight3.IN36
B[29] => ShiftLeft1.IN35
B[29] => ShiftRight2.IN35
B[29] => ShiftRight3.IN35
B[30] => ShiftLeft1.IN34
B[30] => ShiftRight2.IN34
B[30] => ShiftRight3.IN34
B[31] => ShiftLeft1.IN33
B[31] => ShiftRight2.IN33
B[31] => ShiftRight3.IN33
C[0] => ShiftLeft0.IN37
C[0] => ShiftRight0.IN37
C[0] => ShiftRight1.IN37
C[1] => ShiftLeft0.IN36
C[1] => ShiftRight0.IN36
C[1] => ShiftRight1.IN36
C[2] => ShiftLeft0.IN35
C[2] => ShiftRight0.IN35
C[2] => ShiftRight1.IN35
C[3] => ShiftLeft0.IN34
C[3] => ShiftRight0.IN34
C[3] => ShiftRight1.IN34
C[4] => ShiftLeft0.IN33
C[4] => ShiftRight0.IN33
C[4] => ShiftRight1.IN33
OUT_1[0] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[1] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[2] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[3] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[4] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[6] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[7] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[8] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[9] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[10] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[11] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[12] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[13] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[14] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[15] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[16] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[17] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[18] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[19] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[20] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[21] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[22] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[23] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[24] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[25] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[26] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[27] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[28] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[29] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
|assignment2|seven_seg_4digit:display
num[0] => num[0].IN1
num[1] => num[1].IN1
num[2] => num[2].IN1
num[3] => num[3].IN1
num[4] => num[4].IN1
num[5] => num[5].IN1
num[6] => num[6].IN1
num[7] => num[7].IN1
num[8] => num[8].IN1
num[9] => num[9].IN1
num[10] => num[10].IN1
num[11] => num[11].IN1
num[12] => num[12].IN1
num[13] => num[13].IN1
num[14] => num[14].IN1
num[15] => num[15].IN1
segments0[0] <= seven_seg:digit0.segments
segments0[1] <= seven_seg:digit0.segments
segments0[2] <= seven_seg:digit0.segments
segments0[3] <= seven_seg:digit0.segments
segments0[4] <= seven_seg:digit0.segments
segments0[5] <= seven_seg:digit0.segments
segments0[6] <= seven_seg:digit0.segments
segments0[7] <= seven_seg:digit0.segments
segments1[0] <= seven_seg:digit1.segments
segments1[1] <= seven_seg:digit1.segments
segments1[2] <= seven_seg:digit1.segments
segments1[3] <= seven_seg:digit1.segments
segments1[4] <= seven_seg:digit1.segments
segments1[5] <= seven_seg:digit1.segments
segments1[6] <= seven_seg:digit1.segments
segments1[7] <= seven_seg:digit1.segments
segments2[0] <= seven_seg:digit2.segments
segments2[1] <= seven_seg:digit2.segments
segments2[2] <= seven_seg:digit2.segments
segments2[3] <= seven_seg:digit2.segments
segments2[4] <= seven_seg:digit2.segments
segments2[5] <= seven_seg:digit2.segments
segments2[6] <= seven_seg:digit2.segments
segments2[7] <= seven_seg:digit2.segments
segments3[0] <= seven_seg:digit3.segments
segments3[1] <= seven_seg:digit3.segments
segments3[2] <= seven_seg:digit3.segments
segments3[3] <= seven_seg:digit3.segments
segments3[4] <= seven_seg:digit3.segments
segments3[5] <= seven_seg:digit3.segments
segments3[6] <= seven_seg:digit3.segments
segments3[7] <= seven_seg:digit3.segments
|assignment2|seven_seg_4digit:display|seven_seg:digit0
num[0] => Decoder0.IN3
num[0] => Mux0.IN19
num[0] => Mux1.IN19
num[0] => Mux2.IN19
num[0] => Mux3.IN19
num[0] => Mux4.IN19
num[0] => Mux5.IN19
num[1] => Decoder0.IN2
num[1] => Mux0.IN18
num[1] => Mux1.IN18
num[1] => Mux2.IN18
num[1] => Mux3.IN18
num[1] => Mux4.IN18
num[1] => Mux5.IN18
num[2] => Decoder0.IN1
num[2] => Mux0.IN17
num[2] => Mux1.IN17
num[2] => Mux2.IN17
num[2] => Mux3.IN17
num[2] => Mux4.IN17
num[2] => Mux5.IN17
num[3] => Decoder0.IN0
num[3] => Mux0.IN16
num[3] => Mux1.IN16
num[3] => Mux2.IN16
num[3] => Mux3.IN16
num[3] => Mux4.IN16
num[3] => Mux5.IN16
rbi_inv[0] => Mux0.IN15
rbi_inv[0] => Mux1.IN15
rbi_inv[0] => Mux2.IN15
rbi_inv[0] => Mux3.IN15
rbi_inv[0] => Mux4.IN15
rbi_inv[0] => Mux5.IN15
rbi_inv[0] => segments.DATAB
segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE
segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
|assignment2|seven_seg_4digit:display|seven_seg:digit1
num[0] => Decoder0.IN3
num[0] => Mux0.IN19
num[0] => Mux1.IN19
num[0] => Mux2.IN19
num[0] => Mux3.IN19
num[0] => Mux4.IN19
num[0] => Mux5.IN19
num[1] => Decoder0.IN2
num[1] => Mux0.IN18
num[1] => Mux1.IN18
num[1] => Mux2.IN18
num[1] => Mux3.IN18
num[1] => Mux4.IN18
num[1] => Mux5.IN18
num[2] => Decoder0.IN1
num[2] => Mux0.IN17
num[2] => Mux1.IN17
num[2] => Mux2.IN17
num[2] => Mux3.IN17
num[2] => Mux4.IN17
num[2] => Mux5.IN17
num[3] => Decoder0.IN0
num[3] => Mux0.IN16
num[3] => Mux1.IN16
num[3] => Mux2.IN16
num[3] => Mux3.IN16
num[3] => Mux4.IN16
num[3] => Mux5.IN16
rbi_inv[0] => Mux0.IN15
rbi_inv[0] => Mux1.IN15
rbi_inv[0] => Mux2.IN15
rbi_inv[0] => Mux3.IN15
rbi_inv[0] => Mux4.IN15
rbi_inv[0] => Mux5.IN15
rbi_inv[0] => segments.DATAB
segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE
segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
|assignment2|seven_seg_4digit:display|seven_seg:digit2
num[0] => Decoder0.IN3
num[0] => Mux0.IN19
num[0] => Mux1.IN19
num[0] => Mux2.IN19
num[0] => Mux3.IN19
num[0] => Mux4.IN19
num[0] => Mux5.IN19
num[1] => Decoder0.IN2
num[1] => Mux0.IN18
num[1] => Mux1.IN18
num[1] => Mux2.IN18
num[1] => Mux3.IN18
num[1] => Mux4.IN18
num[1] => Mux5.IN18
num[2] => Decoder0.IN1
num[2] => Mux0.IN17
num[2] => Mux1.IN17
num[2] => Mux2.IN17
num[2] => Mux3.IN17
num[2] => Mux4.IN17
num[2] => Mux5.IN17
num[3] => Decoder0.IN0
num[3] => Mux0.IN16
num[3] => Mux1.IN16
num[3] => Mux2.IN16
num[3] => Mux3.IN16
num[3] => Mux4.IN16
num[3] => Mux5.IN16
rbi_inv[0] => Mux0.IN15
rbi_inv[0] => Mux1.IN15
rbi_inv[0] => Mux2.IN15
rbi_inv[0] => Mux3.IN15
rbi_inv[0] => Mux4.IN15
rbi_inv[0] => Mux5.IN15
rbi_inv[0] => segments.DATAB
segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE
segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
|assignment2|seven_seg_4digit:display|seven_seg:digit3
num[0] => Decoder0.IN3
num[0] => Mux0.IN19
num[0] => Mux1.IN19
num[0] => Mux2.IN19
num[0] => Mux3.IN19
num[0] => Mux4.IN19
num[0] => Mux5.IN19
num[1] => Decoder0.IN2
num[1] => Mux0.IN18
num[1] => Mux1.IN18
num[1] => Mux2.IN18
num[1] => Mux3.IN18
num[1] => Mux4.IN18
num[1] => Mux5.IN18
num[2] => Decoder0.IN1
num[2] => Mux0.IN17
num[2] => Mux1.IN17
num[2] => Mux2.IN17
num[2] => Mux3.IN17
num[2] => Mux4.IN17
num[2] => Mux5.IN17
num[3] => Decoder0.IN0
num[3] => Mux0.IN16
num[3] => Mux1.IN16
num[3] => Mux2.IN16
num[3] => Mux3.IN16
num[3] => Mux4.IN16
num[3] => Mux5.IN16
rbi_inv[0] => Mux0.IN15
rbi_inv[0] => Mux1.IN15
rbi_inv[0] => Mux2.IN15
rbi_inv[0] => Mux3.IN15
rbi_inv[0] => Mux4.IN15
rbi_inv[0] => Mux5.IN15
rbi_inv[0] => segments.DATAB
segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE
segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
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