riley 3e8aa911ce Made RSIOut the LSB to correspond with wiring configuration

2026-09-03 16:56:11 +10:00

..

alu.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

asu.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

instruction_classifier.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

lu.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

seven_seg.sv

Made RSIOut the LSB to correspond with wiring configuration

2026-09-03 16:56:11 +10:00

shifter.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00