24 lines
1.1 KiB
Systemverilog
24 lines
1.1 KiB
Systemverilog
module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
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always_comb begin
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case (num)
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4'b0000: segments = (rbi_inv) ? ~(8'b11111101) : ~(8'b00000000);
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4'b0001: segments = ~(8'b01100001);
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4'b0010: segments = ~(8'b11011011);
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4'b0011: segments = ~(8'b11110011);
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4'b0100: segments = ~(8'b01100111);
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4'b0101: segments = ~(8'b10110111);
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4'b0110: segments = ~(8'b10111111);
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4'b0111: segments = ~(8'b11100001);
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4'b1000: segments = ~(8'b11111111);
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4'b1001: segments = ~(8'b11100111);
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4'b1010: segments = ~(8'b11101111);
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4'b1011: segments = ~(8'b00111111);
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4'b1100: segments = ~(8'b10011101);
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4'b1101: segments = ~(8'b01111011);
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4'b1110: segments = ~(8'b10011111);
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4'b1111: segments = ~(8'b10001111);
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default: segments = ~(8'bxxxxxxxx);
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endcase
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end
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endmodule
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