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FPGA_Uni/Quartus/A1_Q1/output_files/seven_seg.map.summary
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Analysis & Synthesis Status : Successful - Thu Sep 3 16:28:16 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : seven_seg
Top-level Entity Name : seven_seg
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 0
Total pins : 13
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 0
Total DLLs : 0