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FPGA_Uni/Quartus/A1_Q3/db/asu.hier_info
T

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|asu
op[0] => operand[0].IN0
op[0] => operand[1].IN0
op[0] => operand[2].IN0
op[0] => operand[3].IN0
op[0] => _.DATAB
A[0] => _.DATAD
A[1] => _.DATAD
A[2] => _.DATAD
A[3] => OUT_CIN.IN1
A[3] => _.DATAD
B[0] => operand[0].IN1
B[1] => operand[1].IN1
B[2] => operand[2].IN1
B[3] => operand[3].IN1
OUT_1[0] << _.SUM_OUT
OUT_1[1] << _.SUM_OUT
OUT_1[2] << _.SUM_OUT
OUT_1[3] << _.SUM_OUT
COUT[0] << _.SUM_OUT
OUT_CIN[0] << OUT_CIN.DB_MAX_OUTPUT_PORT_TYPE