208 lines
19 KiB
Plaintext
208 lines
19 KiB
Plaintext
Analysis & Synthesis report for assignment2
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Thu Oct 15 15:04:20 2026
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Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2025 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus Prime License Agreement,
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the Altera IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Altera and sold by Altera or its authorized distributors. Please
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refer to the Altera Software License Subscription Agreements
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on the Quartus Prime software download page.
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+-------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+-----------------------------+-------------------------------------------------+
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; Analysis & Synthesis Status ; Failed - Thu Oct 15 15:04:20 2026 ;
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; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
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; Revision Name ; assignment2 ;
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; Top-level Entity Name ; assignment2 ;
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; Family ; Cyclone V ;
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; Logic utilization (in ALMs) ; N/A until Partition Merge ;
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; Total registers ; N/A until Partition Merge ;
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; Total pins ; N/A until Partition Merge ;
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; Total virtual pins ; N/A until Partition Merge ;
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; Total block memory bits ; N/A until Partition Merge ;
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; Total PLLs ; N/A until Partition Merge ;
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; Total DLLs ; N/A until Partition Merge ;
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+-----------------------------+-------------------------------------------------+
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+---------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+---------------------------------------------------------------------------------+--------------------+--------------------+
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; Option ; Setting ; Default Value ;
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+---------------------------------------------------------------------------------+--------------------+--------------------+
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; Device ; 5CGXFC5C6F27C7 ; ;
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; Top-level entity name ; assignment2 ; assignment2 ;
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; Family name ; Cyclone V ; Cyclone V ;
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; Maximum processors allowed for parallel compilation ; 2 ; ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Restructure Multiplexers ; Auto ; Auto ;
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; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
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; Create Debugging Nodes for IP Cores ; Off ; Off ;
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; Preserve fewer node names ; On ; On ;
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; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
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; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
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; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
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; State Machine Processing ; Auto ; Auto ;
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; Safe State Machine ; Off ; Off ;
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; Extract Verilog State Machines ; On ; On ;
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; Extract VHDL State Machines ; On ; On ;
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; Ignore Verilog initial constructs ; Off ; Off ;
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; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
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; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
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; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
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; Infer RAMs from Raw Logic ; On ; On ;
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; Parallel Synthesis ; On ; On ;
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; DSP Block Balancing ; Auto ; Auto ;
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; NOT Gate Push-Back ; On ; On ;
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; Power-Up Don't Care ; On ; On ;
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; Remove Redundant Logic Cells ; Off ; Off ;
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; Remove Duplicate Registers ; On ; On ;
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; Ignore CARRY Buffers ; Off ; Off ;
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; Ignore CASCADE Buffers ; Off ; Off ;
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; Ignore GLOBAL Buffers ; Off ; Off ;
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; Ignore ROW GLOBAL Buffers ; Off ; Off ;
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; Ignore LCELL Buffers ; Off ; Off ;
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; Ignore SOFT Buffers ; On ; On ;
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; Limit AHDL Integers to 32 Bits ; Off ; Off ;
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; Optimization Technique ; Balanced ; Balanced ;
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; Carry Chain Length ; 70 ; 70 ;
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; Auto Carry Chains ; On ; On ;
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; Auto Open-Drain Pins ; On ; On ;
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; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
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; Auto ROM Replacement ; On ; On ;
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; Auto RAM Replacement ; On ; On ;
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; Auto DSP Block Replacement ; On ; On ;
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; Auto Shift Register Replacement ; Auto ; Auto ;
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; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
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; Auto Clock Enable Replacement ; On ; On ;
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; Strict RAM Replacement ; Off ; Off ;
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; Allow Synchronous Control Signals ; On ; On ;
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; Force Use of Synchronous Clear Signals ; Off ; Off ;
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; Auto Resource Sharing ; Off ; Off ;
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; Allow Any RAM Size For Recognition ; Off ; Off ;
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; Allow Any ROM Size For Recognition ; Off ; Off ;
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; Allow Any Shift Register Size For Recognition ; Off ; Off ;
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; Use LogicLock Constraints during Resource Balancing ; On ; On ;
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; Ignore translate_off and synthesis_off directives ; Off ; Off ;
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; Timing-Driven Synthesis ; On ; On ;
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; Report Parameter Settings ; On ; On ;
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; Report Source Assignments ; On ; On ;
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; Report Connectivity Checks ; On ; On ;
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; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
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; Synchronization Register Chain Length ; 3 ; 3 ;
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; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
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; HDL message level ; Level2 ; Level2 ;
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; Suppress Register Optimization Related Messages ; Off ; Off ;
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; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
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; Clock MUX Protection ; On ; On ;
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; Auto Gated Clock Conversion ; Off ; Off ;
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; Block Design Naming ; Auto ; Auto ;
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; SDC constraint protection ; Off ; Off ;
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; Synthesis Effort ; Auto ; Auto ;
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; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
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; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
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; Analysis & Synthesis Message Level ; Medium ; Medium ;
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; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
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; Resource Aware Inference For Block RAM ; On ; On ;
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; Automatic Parallel Synthesis ; On ; On ;
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; Partial Reconfiguration Bitstream ID ; Off ; Off ;
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+---------------------------------------------------------------------------------+--------------------+--------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 2 ;
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; ; ;
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; Average used ; 1.00 ;
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; Maximum used ; 1 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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+----------------------------+-------------+
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+-------------------------------+
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; Analysis & Synthesis Messages ;
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+-------------------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime Analysis & Synthesis
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Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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Info: Processing started: Thu Oct 15 15:04:10 2026
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Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2
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Info (20032): Parallel compilation is enabled and will use up to 2 processors
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Info (12021): Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv
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Info (12023): Found entity 1: rom File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 4
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Info (12023): Found entity 2: ram File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 4
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Info (12023): Found entity 3: register_file File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 4
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Info (12023): Found entity 4: instruction_counter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv Line: 4
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Info (12023): Found entity 5: instruction_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv Line: 3
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Info (12023): Found entity 6: instruction_module_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv Line: 4
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Info (12023): Found entity 7: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 4
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Info (12023): Found entity 8: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3
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Info (12023): Found entity 9: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9
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Info (12023): Found entity 10: shifter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv Line: 3
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Info (12023): Found entity 11: sign_extender File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv Line: 4
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Info (12023): Found entity 12: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv Line: 3
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Info (12023): Found entity 13: seven_seg_4digit File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv Line: 5
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Info (12023): Found entity 14: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 16
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Info (12127): Elaborating entity "assignment2" for the top level hierarchy
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Warning (10230): Verilog HDL assignment warning at assignment2.sv(100): truncated value with size 32 to match size of target (10) File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 100
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Warning (10030): Net "flags[2]" at assignment2.sv(55) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 55
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Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 62
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Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 64
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Warning (10850): Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range [0:1023] File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 16
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Warning (10030): Net "mem.data_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
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Warning (10030): Net "mem.waddr_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
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Warning (10030): Net "mem.we_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
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Info (12128): Elaborating entity "ram" for hierarchy "ram:RAM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 67
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Warning (10230): Verilog HDL assignment warning at ram.sv(23): truncated value with size 32 to match size of target (8) File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 23
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Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 69
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Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 76
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Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 85
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Warning (10855): Verilog HDL warning at register_file.sv(14): initial value for variable regs should be constant File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 14
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Info (12128): Elaborating entity "sign_extender" for hierarchy "sign_extender:SIGNEXT" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 88
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Error (10043): Verilog HDL unsupported feature error at sign_extender.sv(11): Procedural Continuous Assignment to register is not supported File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv Line: 11
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Error (12152): Can't elaborate user hierarchy "sign_extender:SIGNEXT" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 88
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Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 8 warnings
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Error: Peak virtual memory: 412 megabytes
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Error: Processing ended: Thu Oct 15 15:04:21 2026
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Error: Elapsed time: 00:00:11
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Error: Total CPU time (on all processors): 00:00:24
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