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FPGA_Uni
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0ef2aeeb482638e7a79443524f339d98c248b045
FPGA_Uni
/
Quartus
/
A1_Q1
/
db
/
seven_seg.rtlv.hdb
T
TroubleElectrical
afa8d9d4db
Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments
2026-09-15 21:08:40 +10:00
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