riley 4c7e2ff085 Fixed instruction width issue in ROM. Stripped all comments to form minimal HEX file to rule out possible parser issues.

2026-10-16 11:29:04 +11:00

..

bin

Fixed instruction width issue in ROM. Stripped all comments to form minimal HEX file to rule out possible parser issues.

2026-10-16 11:29:04 +11:00

src

Realized that, while the assembled is not binary, it is still loadable by verilog.

2026-10-08 14:18:11 +11:00