298 lines
23 KiB
Plaintext
298 lines
23 KiB
Plaintext
Analysis & Synthesis report for shifter
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Tue Sep 15 19:48:53 2026
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Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Source Files Read
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6. Analysis & Synthesis Resource Usage Summary
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7. Analysis & Synthesis Resource Utilization by Entity
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8. General Register Statistics
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9. Parameter Settings for User Entity Instance: Top-level Entity: |shifter
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10. Post-Synthesis Netlist Statistics for Top Partition
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11. Elapsed Time Per Partition
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12. Analysis & Synthesis Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2025 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus Prime License Agreement,
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the Altera IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Altera and sold by Altera or its authorized distributors. Please
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refer to the Altera Software License Subscription Agreements
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on the Quartus Prime software download page.
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+-----------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+---------------------------------+-------------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Tue Sep 15 19:48:53 2026 ;
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; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
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; Revision Name ; shifter ;
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; Top-level Entity Name ; shifter ;
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; Family ; Cyclone V ;
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; Logic utilization (in ALMs) ; N/A ;
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; Total registers ; 0 ;
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; Total pins ; 17 ;
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; Total virtual pins ; 0 ;
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; Total block memory bits ; 0 ;
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; Total DSP Blocks ; 0 ;
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; Total HSSI RX PCSs ; 0 ;
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; Total HSSI PMA RX Deserializers ; 0 ;
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; Total HSSI TX PCSs ; 0 ;
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; Total HSSI PMA TX Serializers ; 0 ;
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; Total PLLs ; 0 ;
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; Total DLLs ; 0 ;
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+---------------------------------+-------------------------------------------------+
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+---------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+---------------------------------------------------------------------------------+--------------------+--------------------+
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; Option ; Setting ; Default Value ;
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+---------------------------------------------------------------------------------+--------------------+--------------------+
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; Device ; 5CGXFC5C6F27C7 ; ;
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; Top-level entity name ; shifter ; shifter ;
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; Family name ; Cyclone V ; Cyclone V ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Restructure Multiplexers ; Auto ; Auto ;
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; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
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; Create Debugging Nodes for IP Cores ; Off ; Off ;
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; Preserve fewer node names ; On ; On ;
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; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
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; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
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; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
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; State Machine Processing ; Auto ; Auto ;
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; Safe State Machine ; Off ; Off ;
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; Extract Verilog State Machines ; On ; On ;
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; Extract VHDL State Machines ; On ; On ;
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; Ignore Verilog initial constructs ; Off ; Off ;
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; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
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; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
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; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
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; Infer RAMs from Raw Logic ; On ; On ;
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; Parallel Synthesis ; On ; On ;
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; DSP Block Balancing ; Auto ; Auto ;
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; NOT Gate Push-Back ; On ; On ;
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; Power-Up Don't Care ; On ; On ;
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; Remove Redundant Logic Cells ; Off ; Off ;
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; Remove Duplicate Registers ; On ; On ;
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; Ignore CARRY Buffers ; Off ; Off ;
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; Ignore CASCADE Buffers ; Off ; Off ;
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; Ignore GLOBAL Buffers ; Off ; Off ;
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; Ignore ROW GLOBAL Buffers ; Off ; Off ;
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; Ignore LCELL Buffers ; Off ; Off ;
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; Ignore SOFT Buffers ; On ; On ;
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; Limit AHDL Integers to 32 Bits ; Off ; Off ;
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; Optimization Technique ; Balanced ; Balanced ;
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; Carry Chain Length ; 70 ; 70 ;
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; Auto Carry Chains ; On ; On ;
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; Auto Open-Drain Pins ; On ; On ;
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; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
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; Auto ROM Replacement ; On ; On ;
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; Auto RAM Replacement ; On ; On ;
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; Auto DSP Block Replacement ; On ; On ;
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; Auto Shift Register Replacement ; Auto ; Auto ;
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; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
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; Auto Clock Enable Replacement ; On ; On ;
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; Strict RAM Replacement ; Off ; Off ;
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; Allow Synchronous Control Signals ; On ; On ;
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; Force Use of Synchronous Clear Signals ; Off ; Off ;
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; Auto Resource Sharing ; Off ; Off ;
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; Allow Any RAM Size For Recognition ; Off ; Off ;
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; Allow Any ROM Size For Recognition ; Off ; Off ;
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; Allow Any Shift Register Size For Recognition ; Off ; Off ;
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; Use LogicLock Constraints during Resource Balancing ; On ; On ;
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; Ignore translate_off and synthesis_off directives ; Off ; Off ;
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; Timing-Driven Synthesis ; On ; On ;
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; Report Parameter Settings ; On ; On ;
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; Report Source Assignments ; On ; On ;
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; Report Connectivity Checks ; On ; On ;
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; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
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; Synchronization Register Chain Length ; 3 ; 3 ;
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; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
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; HDL message level ; Level2 ; Level2 ;
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; Suppress Register Optimization Related Messages ; Off ; Off ;
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; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
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; Clock MUX Protection ; On ; On ;
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; Auto Gated Clock Conversion ; Off ; Off ;
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; Block Design Naming ; Auto ; Auto ;
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; SDC constraint protection ; Off ; Off ;
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; Synthesis Effort ; Auto ; Auto ;
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; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
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; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
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; Analysis & Synthesis Message Level ; Medium ; Medium ;
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; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
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; Resource Aware Inference For Block RAM ; On ; On ;
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; Automatic Parallel Synthesis ; On ; On ;
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; Partial Reconfiguration Bitstream ID ; Off ; Off ;
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+---------------------------------------------------------------------------------+--------------------+--------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 2 ;
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; ; ;
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; Average used ; 1.00 ;
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; Maximum used ; 1 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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+----------------------------+-------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Source Files Read ;
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+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+---------+
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; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
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+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+---------+
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; ../../modules/shifter.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv ; ;
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+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+---------+
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+----------------------------------------------------------+
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; Analysis & Synthesis Resource Usage Summary ;
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+---------------------------------------------+------------+
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; Resource ; Usage ;
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+---------------------------------------------+------------+
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; Estimate of Logic utilization (ALMs needed) ; 23 ;
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; ; ;
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; Combinational ALUT usage for logic ; 32 ;
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; -- 7 input functions ; 1 ;
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; -- 6 input functions ; 13 ;
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; -- 5 input functions ; 5 ;
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; -- 4 input functions ; 6 ;
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; -- <=3 input functions ; 7 ;
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; ; ;
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; Dedicated logic registers ; 0 ;
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; ; ;
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; I/O pins ; 17 ;
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; ; ;
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; Total DSP Blocks ; 0 ;
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; ; ;
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; Maximum fan-out node ; A[3]~input ;
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; Maximum fan-out ; 15 ;
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; Total fan-out ; 173 ;
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; Average fan-out ; 2.62 ;
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+---------------------------------------------+------------+
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Resource Utilization by Entity ;
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+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
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; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
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; |shifter ; 32 (32) ; 0 (0) ; 0 ; 0 ; 17 ; 0 ; |shifter ; shifter ; work ;
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+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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+------------------------------------------------------+
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; General Register Statistics ;
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+----------------------------------------------+-------+
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; Statistic ; Value ;
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+----------------------------------------------+-------+
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; Total registers ; 0 ;
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; Number of registers using Synchronous Clear ; 0 ;
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; Number of registers using Synchronous Load ; 0 ;
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; Number of registers using Asynchronous Clear ; 0 ;
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; Number of registers using Asynchronous Load ; 0 ;
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; Number of registers using Clock Enable ; 0 ;
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; Number of registers using Preset ; 0 ;
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+----------------------------------------------+-------+
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+-------------------------------------------------------------------------+
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; Parameter Settings for User Entity Instance: Top-level Entity: |shifter ;
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+----------------+-------+------------------------------------------------+
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; Parameter Name ; Value ; Type ;
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+----------------+-------+------------------------------------------------+
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; width ; 2 ; Signed Integer ;
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+----------------+-------+------------------------------------------------+
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Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
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+-----------------------------------------------------+
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; Post-Synthesis Netlist Statistics for Top Partition ;
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+-----------------------+-----------------------------+
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; Type ; Count ;
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+-----------------------+-----------------------------+
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; arriav_lcell_comb ; 32 ;
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; extend ; 1 ;
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; 7 data inputs ; 1 ;
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; normal ; 31 ;
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; 2 data inputs ; 3 ;
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; 3 data inputs ; 4 ;
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; 4 data inputs ; 6 ;
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; 5 data inputs ; 5 ;
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; 6 data inputs ; 13 ;
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; boundary_port ; 17 ;
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; ; ;
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; Max LUT depth ; 4.00 ;
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; Average LUT depth ; 3.13 ;
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+-----------------------+-----------------------------+
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+-------------------------------+
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; Elapsed Time Per Partition ;
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+----------------+--------------+
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; Partition Name ; Elapsed Time ;
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+----------------+--------------+
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; Top ; 00:00:00 ;
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+----------------+--------------+
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+-------------------------------+
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; Analysis & Synthesis Messages ;
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+-------------------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime Analysis & Synthesis
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Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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Info: Processing started: Tue Sep 15 19:48:42 2026
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Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
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Info (12021): Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv
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Info (12023): Found entity 1: shifter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv Line: 3
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Info (12127): Elaborating entity "shifter" for the top level hierarchy
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Info (286030): Timing-Driven Synthesis is running
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Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
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Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
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Info (21057): Implemented 49 device resources after synthesis - the final resource count might be different
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Info (21058): Implemented 13 input pins
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Info (21059): Implemented 4 output pins
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Info (21061): Implemented 32 logic cells
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Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 433 megabytes
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Info: Processing ended: Tue Sep 15 19:48:53 2026
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Info: Elapsed time: 00:00:11
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Info: Total CPU time (on all processors): 00:00:25
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