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05361dcf70f418e7ef77544e5abba5ab0f40b55e
FPGA_Uni
/
Quartus
/
A1_Q3
T
History
TroubleElectrical
05361dcf70
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
..
db
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
incremental_db
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
output_files
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
simulation
/questa
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
A1_Q3.qpf
Added projects for A1 q2 to q6
2026-09-04 13:12:33 +10:00
asu.qsf
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
asu.qws
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
c5_pin_model_dump.txt
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
