122 lines
5.0 KiB
Systemverilog
122 lines
5.0 KiB
Systemverilog
`include "asu.sv"
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module asu_tb #(width=8)();
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logic [0:0] op;
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logic [width-1:0] A;
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logic [width-1:0] B;
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logic [width-1:0] C;
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logic [0:0] Cout;
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logic [0:0] Cin;
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logic [width-1:0] C_exp;
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logic [0:0] Cout_exp;
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logic [0:0] Cin_exp; // TODO
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asu #($clog2(width)) dut(op, A, B, C, Cout, Cin);
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integer error_count;
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initial begin
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error_count = 0;
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$display("Beginning ASU tests");
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// Test basic addition of 0+1 = 1
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op = 1'b0;
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A = {width{1'b0}};
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B = { {(width-1){1'b0}}, 1'b1};
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C_exp = { {(width-1){1'b0}}, 1'b1};
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Cout_exp = 1'b0;
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Cin_exp = 1'b0;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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// Test underflow from 0-1 = UINTMAX
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op = 1'b1;
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C_exp = {(width){1'b1}};
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Cout_exp = 1'b0;
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Cin_exp = 1'b0;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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// Test carry addition of 1+1 = 2
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op = 1'b0;
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A = { {(width-1){1'b0}}, 1'b1};
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B = { {(width-1){1'b0}}, 1'b1};
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C_exp = { {(width-2){1'b0}}, 2'b10};
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Cout_exp = 1'b0;
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Cin_exp = 1'b0;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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// Test overflow from UINTMAX+1 = 0
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A = {(width){1'b1}}; // UINTMAX
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B = { {(width-1){1'b0}}, 1'b1}; // 1
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C_exp = {(width){1'b0}};
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Cout_exp = 1'b1;
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Cin_exp = 1'b1;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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// Tests INTMAX+1
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op = 1'b0;
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A = {1'b0, {(width-1){1'b1}}}; // INTMAX
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B = {{(width-1){1'b0}}, 1'b1}; // 1
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C_exp = {1'b1, {(width-1){1'b0}}}; // -INTMAX
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Cin_exp = 1'b1;
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Cout_exp = 1'b0;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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op = 1'b0;
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A = {1'b1, {(width-1){1'b0}}}; // -INTMAX
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B = {1'b1, {(width-1){1'b0}}}; // -INTMAX
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C_exp = {width{1'b0}}; // 0
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Cin_exp = 1'b0;
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Cout_exp = 1'b1;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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op = 1'b1;
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A = {1'b0, {(width-1){1'b1}}}; // INTMAX
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B = {1'b1, {(width-1){1'b0}}}; // -INTMAX
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C_exp = {width{1'b1}}; // -1
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Cin_exp = 1'b1;
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Cout_exp = 1'b0;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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op = 1'b1;
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A = {1'b1, {(width-1){1'b0}}}; // -INTMAX
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B = {{(width-1){1'b0}}, 1'b1}; // 1
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C_exp = {1'b0, {(width-1){1'b1}}}; // INTMAX
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Cin_exp = 1'b0;
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Cout_exp = 1'b1;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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if (error_count == 0) $display("\x1b[38;5;10mAll ASU tests passing\x1b[m");
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else $display("\x1b[38;5;9m%0d ASU test(s) failing\x1b[m", error_count);
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end
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endmodule |