This website requires JavaScript.
Explore
Help
Sign In
TroubleElectrical
/
FPGA_Uni
Watch
1
Star
0
Fork
0
Code
Issues
1
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
Files
04d1d3e2fe5a442ae7af9512e09878c0ef118b12
FPGA_Uni
/
Quartus
/
A1_Q6
T
History
TroubleElectrical
b49e294b7d
Updated register_file.sv with proper naming scheme and 32bit width
2026-10-08 15:10:40 +11:00
..
db
Updated register_file.sv with proper naming scheme and 32bit width
2026-10-08 15:10:40 +11:00
incremental_db
Implemented instruction classifier on board (Q6) and added blank submission files (for now)
2026-09-15 20:00:35 +10:00
output_files
Implemented instruction classifier on board (Q6) and added blank submission files (for now)
2026-09-15 20:00:35 +10:00
simulation
/questa
Implemented instruction classifier on board (Q6) and added blank submission files (for now)
2026-09-15 20:00:35 +10:00
A1_Q6.qpf
Added projects for A1 q2 to q6
2026-09-04 13:12:33 +10:00
c5_pin_model_dump.txt
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
instruction_classifier.qsf
Implemented instruction classifier on board (Q6) and added blank submission files (for now)
2026-09-15 20:00:35 +10:00
instruction_classifier.qws
Updated register_file.sv with proper naming scheme and 32bit width
2026-10-08 15:10:40 +11:00