Files
FPGA_Uni/ModelSim/tests.sv
T

6 lines
189 B
Systemverilog

`include "tests/seven_seg_tb.sv"
`include "tests/lu_tb.sv"
`include "tests/asu_tb.sv"
`include "tests/instruction_classifier_tb.sv"
`include "tests/shifter_tb.sv"
`include "tests/alu_tb.sv"