19 lines
569 B
Systemverilog
19 lines
569 B
Systemverilog
`ifndef SHIFTER_H_SV
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`define SHIFTER_H_SV
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module shifter #(width=2)(input logic [2:0] op,
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input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C,
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output logic[2**width-1:0] OUT_1);
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always_comb begin
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case (op)
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3'b000: OUT_1 = A << C;
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3'b001: OUT_1 = A >> C;
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3'b011: OUT_1 = $signed(A) >>> C;
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3'b100: OUT_1 = A << B;
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3'b101: OUT_1 = A >> B;
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3'b111: OUT_1 = $signed(A) >>> B;
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default:OUT_1 = A;
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endcase
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end
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endmodule
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`endif |