module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
        always_comb begin
           case (num)
               4'b0000: segments = (rbi_inv) ? ~(8'b11111101) : ~(8'b00000000);
               4'b0001: segments = ~(8'b01100001);
               4'b0010: segments = ~(8'b11011011);
               4'b0011: segments = ~(8'b11110011);
               4'b0100: segments = ~(8'b01100111);
               4'b0101: segments = ~(8'b10110111);
               4'b0110: segments = ~(8'b10111111);
               4'b0111: segments = ~(8'b11100001);
               4'b1000: segments = ~(8'b11111111);
               4'b1001: segments = ~(8'b11100111);
               4'b1010: segments = ~(8'b11101111);
               4'b1011: segments = ~(8'b00111111);
               4'b1100: segments = ~(8'b10011101);
               4'b1101: segments = ~(8'b01111011);
               4'b1110: segments = ~(8'b10011111);
               4'b1111: segments = ~(8'b10001111);
               default: segments = ~(8'bxxxxxxxx);
           endcase     
        end
endmodule