# -------------------------------------------------------------------------- #
#
# Copyright (C) 2025  Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Altera and sold by Altera or its authorized distributors.  Please
# refer to the Altera Software License Subscription Agreements 
# on the Quartus Prime software download page.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
# Date created = 13:06:02  September 04, 2026
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		alu_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
set_global_assignment -name TOP_LEVEL_ENTITY alu
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:06:02  SEPTEMBER 04, 2026"
set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition"
set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/alu.sv
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_V19 -to out_seg1[1]
set_location_assignment PIN_V18 -to out_seg1[2]
set_location_assignment PIN_V17 -to out_seg1[3]
set_location_assignment PIN_W18 -to out_seg1[4]
set_location_assignment PIN_Y20 -to out_seg1[5]
set_location_assignment PIN_Y19 -to out_seg1[6]
set_location_assignment PIN_Y18 -to out_seg1[7]
set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[4]
set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[5]
set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[6]
set_instance_assignment -name IO_STANDARD "1.2 V" -to out_seg1[7]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op
set_instance_assignment -name IO_STANDARD "2.5 V" -to flags[0]
set_location_assignment PIN_AE19 -to op[3]
set_location_assignment PIN_Y11 -to op[2]
set_location_assignment PIN_AC10 -to op[1]
set_location_assignment PIN_V10 -to op[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to B[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to B[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to B[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to B[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to B
set_instance_assignment -name IO_STANDARD "1.2 V" -to A[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A
set_location_assignment PIN_AC9 -to B[0]
set_location_assignment PIN_AE10 -to B[1]
set_location_assignment PIN_AD13 -to B[2]
set_location_assignment PIN_AC8 -to B[3]
set_location_assignment PIN_P11 -to A[0]
set_location_assignment PIN_P12 -to A[1]
set_location_assignment PIN_Y15 -to A[2]
set_location_assignment PIN_Y16 -to A[3]
set_location_assignment PIN_J10 -to flags[1]
set_location_assignment PIN_H7 -to flags[0]
set_location_assignment PIN_G7 -to OUT_1[3]
set_location_assignment PIN_F7 -to OUT_1[0]
set_location_assignment PIN_F6 -to OUT_1[1]
set_location_assignment PIN_G6 -to OUT_1[2]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top