# -------------------------------------------------------------------------- # # # Copyright (C) 2025 Altera Corporation. All rights reserved. # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and any partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, the Altera Quartus Prime License Agreement, # the Altera IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by # Altera and sold by Altera or its authorized distributors. Please # refer to the Altera Software License Subscription Agreements # on the Quartus Prime software download page. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition # Date created = 16:08:41 September 03, 2026 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # seven_seg_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Intel recommends that you do not modify this file. This # file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CGXFC5C6F27C7 set_global_assignment -name TOP_LEVEL_ENTITY seven_seg_2digit set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:08:41 SEPTEMBER 03, 2026" set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" set_global_assignment -name SYSTEMVERILOG_FILE seven_seg.sv set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[0] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[1] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[2] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[3] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[4] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[5] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[6] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[7] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[0] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[1] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[2] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[3] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[4] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[5] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[6] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[7] set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a set_instance_assignment -name IO_STANDARD "1.2 V" -to b[0] set_instance_assignment -name IO_STANDARD "1.2 V" -to b[1] set_instance_assignment -name IO_STANDARD "1.2 V" -to b[2] set_instance_assignment -name IO_STANDARD "1.2 V" -to a[0] set_instance_assignment -name IO_STANDARD "1.2 V" -to b[3] set_instance_assignment -name IO_STANDARD "1.2 V" -to b set_instance_assignment -name IO_STANDARD "1.2 V" -to a[1] set_instance_assignment -name IO_STANDARD "1.2 V" -to a[2] set_instance_assignment -name IO_STANDARD "1.2 V" -to a[3] set_location_assignment PIN_V19 -to seg_a[1] set_location_assignment PIN_V18 -to seg_a[2] set_location_assignment PIN_V17 -to seg_a[3] set_location_assignment PIN_W18 -to seg_a[4] set_location_assignment PIN_Y20 -to seg_a[5] set_location_assignment PIN_Y19 -to seg_a[6] set_location_assignment PIN_Y18 -to seg_a[7] set_location_assignment PIN_AA18 -to seg_b[1] set_location_assignment PIN_AD26 -to seg_b[2] set_location_assignment PIN_AB19 -to seg_b[3] set_location_assignment PIN_AE26 -to seg_b[4] set_location_assignment PIN_AE25 -to seg_b[5] set_location_assignment PIN_AC19 -to seg_b[6] set_location_assignment PIN_AF24 -to seg_b[7] set_location_assignment PIN_AC9 -to a[0] set_location_assignment PIN_AE10 -to a[1] set_location_assignment PIN_AD13 -to a[2] set_location_assignment PIN_AC8 -to a[3] set_location_assignment PIN_W11 -to b[0] set_location_assignment PIN_AB10 -to b[1] set_location_assignment PIN_V10 -to b[2] set_location_assignment PIN_AC10 -to b[3] set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top