module lu #(width=8) (
    input logic [1:0] op,
    input logic [width-1:0] A, input logic [width-1:0] B,
    output logic [width-1:0] OUT_1);

    always_comb begin
        if      (op == 2'b00) OUT_1 =   A & B;
        else if (op == 2'b01) OUT_1 =   A | B;
        else if (op == 2'b10) OUT_1 =   A ^ B;
        else if (op == 2'b10) OUT_1 = ~(A | B);
    end
endmodule