// Copyright (C) 2025  Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Altera and sold by Altera or its authorized distributors.  Please
// refer to the Altera Software License Subscription Agreements 
// on the Quartus Prime software download page.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"

// DATE "09/10/2026 14:02:02"

// 
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
// 

// 
// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only
// 

`timescale 1 ps/ 1 ps

module asu (
	op,
	A,
	B,
	OUT_1,
	COUT,
	OUT_CIN);
input 	[0:0] op;
input 	[3:0] A;
input 	[3:0] B;
output 	[3:0] OUT_1;
output 	[0:0] COUT;
output 	[0:0] OUT_CIN;

// Design Ports Information
// OUT_1[0]	=>  Location: PIN_F7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// OUT_1[1]	=>  Location: PIN_F6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// OUT_1[2]	=>  Location: PIN_G6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// OUT_1[3]	=>  Location: PIN_G7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// COUT[0]	=>  Location: PIN_J8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// OUT_CIN[0]	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// op[0]	=>  Location: PIN_AE19,	 I/O Standard: 1.2 V,	 Current Strength: Default
// A[3]	=>  Location: PIN_AC8,	 I/O Standard: 1.2 V,	 Current Strength: Default
// B[3]	=>  Location: PIN_AC10,	 I/O Standard: 1.2 V,	 Current Strength: Default
// B[0]	=>  Location: PIN_W11,	 I/O Standard: 1.2 V,	 Current Strength: Default
// A[0]	=>  Location: PIN_AC9,	 I/O Standard: 1.2 V,	 Current Strength: Default
// A[1]	=>  Location: PIN_AE10,	 I/O Standard: 1.2 V,	 Current Strength: Default
// B[1]	=>  Location: PIN_AB10,	 I/O Standard: 1.2 V,	 Current Strength: Default
// A[2]	=>  Location: PIN_AD13,	 I/O Standard: 1.2 V,	 Current Strength: Default
// B[2]	=>  Location: PIN_V10,	 I/O Standard: 1.2 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \~QUARTUS_CREATED_GND~I_combout ;
wire \op[0]~input_o ;
wire \A[0]~input_o ;
wire \B[0]~input_o ;
wire \_~1_sumout ;
wire \A[1]~input_o ;
wire \B[1]~input_o ;
wire \_~2 ;
wire \_~3 ;
wire \_~5_sumout ;
wire \A[2]~input_o ;
wire \B[2]~input_o ;
wire \_~6 ;
wire \_~7 ;
wire \_~9_sumout ;
wire \A[3]~input_o ;
wire \B[3]~input_o ;
wire \_~10 ;
wire \_~11 ;
wire \_~13_sumout ;
wire \_~14 ;
wire \_~15 ;
wire \_~17_sumout ;
wire \OUT_CIN~0_combout ;


// Location: IOOBUF_X14_Y61_N53
cyclonev_io_obuf \OUT_1[0]~output (
	.i(\_~1_sumout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_1[0]),
	.obar());
// synopsys translate_off
defparam \OUT_1[0]~output .bus_hold = "false";
defparam \OUT_1[0]~output .open_drain_output = "false";
defparam \OUT_1[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X15_Y61_N36
cyclonev_io_obuf \OUT_1[1]~output (
	.i(\_~5_sumout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_1[1]),
	.obar());
// synopsys translate_off
defparam \OUT_1[1]~output .bus_hold = "false";
defparam \OUT_1[1]~output .open_drain_output = "false";
defparam \OUT_1[1]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X15_Y61_N53
cyclonev_io_obuf \OUT_1[2]~output (
	.i(\_~9_sumout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_1[2]),
	.obar());
// synopsys translate_off
defparam \OUT_1[2]~output .bus_hold = "false";
defparam \OUT_1[2]~output .open_drain_output = "false";
defparam \OUT_1[2]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X14_Y61_N36
cyclonev_io_obuf \OUT_1[3]~output (
	.i(\_~13_sumout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_1[3]),
	.obar());
// synopsys translate_off
defparam \OUT_1[3]~output .bus_hold = "false";
defparam \OUT_1[3]~output .open_drain_output = "false";
defparam \OUT_1[3]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X14_Y61_N19
cyclonev_io_obuf \COUT[0]~output (
	.i(\_~17_sumout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(COUT[0]),
	.obar());
// synopsys translate_off
defparam \COUT[0]~output .bus_hold = "false";
defparam \COUT[0]~output .open_drain_output = "false";
defparam \COUT[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X10_Y61_N42
cyclonev_io_obuf \OUT_CIN[0]~output (
	.i(\OUT_CIN~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_CIN[0]),
	.obar());
// synopsys translate_off
defparam \OUT_CIN[0]~output .bus_hold = "false";
defparam \OUT_CIN[0]~output .open_drain_output = "false";
defparam \OUT_CIN[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOIBUF_X50_Y0_N35
cyclonev_io_ibuf \op[0]~input (
	.i(op[0]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\op[0]~input_o ));
// synopsys translate_off
defparam \op[0]~input .bus_hold = "false";
defparam \op[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X14_Y0_N35
cyclonev_io_ibuf \A[0]~input (
	.i(A[0]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\A[0]~input_o ));
// synopsys translate_off
defparam \A[0]~input .bus_hold = "false";
defparam \A[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X10_Y0_N41
cyclonev_io_ibuf \B[0]~input (
	.i(B[0]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\B[0]~input_o ));
// synopsys translate_off
defparam \B[0]~input .bus_hold = "false";
defparam \B[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LABCELL_X18_Y4_N30
cyclonev_lcell_comb \_~1 (
// Equation(s):
// \_~1_sumout  = SUM(( !\A[0]~input_o  $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC ))
// \_~2  = CARRY(( !\A[0]~input_o  $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC ))
// \_~3  = SHARE((!\B[0]~input_o  & (\op[0]~input_o )) # (\B[0]~input_o  & ((\A[0]~input_o ))))

	.dataa(gnd),
	.datab(!\op[0]~input_o ),
	.datac(!\A[0]~input_o ),
	.datad(!\B[0]~input_o ),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(),
	.sumout(\_~1_sumout ),
	.cout(\_~2 ),
	.shareout(\_~3 ));
// synopsys translate_off
defparam \_~1 .extended_lut = "off";
defparam \_~1 .lut_mask = 64'h0000330F00000FF0;
defparam \_~1 .shared_arith = "on";
// synopsys translate_on

// Location: IOIBUF_X36_Y0_N52
cyclonev_io_ibuf \A[1]~input (
	.i(A[1]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\A[1]~input_o ));
// synopsys translate_off
defparam \A[1]~input .bus_hold = "false";
defparam \A[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X12_Y0_N35
cyclonev_io_ibuf \B[1]~input (
	.i(B[1]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\B[1]~input_o ));
// synopsys translate_off
defparam \B[1]~input .bus_hold = "false";
defparam \B[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LABCELL_X18_Y4_N33
cyclonev_lcell_comb \_~5 (
// Equation(s):
// \_~5_sumout  = SUM(( !\A[1]~input_o  $ (!\op[0]~input_o  $ (\B[1]~input_o )) ) + ( \_~3  ) + ( \_~2  ))
// \_~6  = CARRY(( !\A[1]~input_o  $ (!\op[0]~input_o  $ (\B[1]~input_o )) ) + ( \_~3  ) + ( \_~2  ))
// \_~7  = SHARE((\A[1]~input_o  & (!\op[0]~input_o  $ (!\B[1]~input_o ))))

	.dataa(!\A[1]~input_o ),
	.datab(!\op[0]~input_o ),
	.datac(!\B[1]~input_o ),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(\_~2 ),
	.sharein(\_~3 ),
	.combout(),
	.sumout(\_~5_sumout ),
	.cout(\_~6 ),
	.shareout(\_~7 ));
// synopsys translate_off
defparam \_~5 .extended_lut = "off";
defparam \_~5 .lut_mask = 64'h0000141400006969;
defparam \_~5 .shared_arith = "on";
// synopsys translate_on

// Location: IOIBUF_X34_Y0_N35
cyclonev_io_ibuf \A[2]~input (
	.i(A[2]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\A[2]~input_o ));
// synopsys translate_off
defparam \A[2]~input .bus_hold = "false";
defparam \A[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X17_Y0_N75
cyclonev_io_ibuf \B[2]~input (
	.i(B[2]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\B[2]~input_o ));
// synopsys translate_off
defparam \B[2]~input .bus_hold = "false";
defparam \B[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LABCELL_X18_Y4_N36
cyclonev_lcell_comb \_~9 (
// Equation(s):
// \_~9_sumout  = SUM(( !\op[0]~input_o  $ (!\A[2]~input_o  $ (\B[2]~input_o )) ) + ( \_~7  ) + ( \_~6  ))
// \_~10  = CARRY(( !\op[0]~input_o  $ (!\A[2]~input_o  $ (\B[2]~input_o )) ) + ( \_~7  ) + ( \_~6  ))
// \_~11  = SHARE((\A[2]~input_o  & (!\op[0]~input_o  $ (!\B[2]~input_o ))))

	.dataa(gnd),
	.datab(!\op[0]~input_o ),
	.datac(!\A[2]~input_o ),
	.datad(!\B[2]~input_o ),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(\_~6 ),
	.sharein(\_~7 ),
	.combout(),
	.sumout(\_~9_sumout ),
	.cout(\_~10 ),
	.shareout(\_~11 ));
// synopsys translate_off
defparam \_~9 .extended_lut = "off";
defparam \_~9 .lut_mask = 64'h0000030C00003CC3;
defparam \_~9 .shared_arith = "on";
// synopsys translate_on

// Location: IOIBUF_X14_Y0_N52
cyclonev_io_ibuf \A[3]~input (
	.i(A[3]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\A[3]~input_o ));
// synopsys translate_off
defparam \A[3]~input .bus_hold = "false";
defparam \A[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X12_Y0_N52
cyclonev_io_ibuf \B[3]~input (
	.i(B[3]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\B[3]~input_o ));
// synopsys translate_off
defparam \B[3]~input .bus_hold = "false";
defparam \B[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LABCELL_X18_Y4_N39
cyclonev_lcell_comb \_~13 (
// Equation(s):
// \_~13_sumout  = SUM(( !\op[0]~input_o  $ (!\A[3]~input_o  $ (\B[3]~input_o )) ) + ( \_~11  ) + ( \_~10  ))
// \_~14  = CARRY(( !\op[0]~input_o  $ (!\A[3]~input_o  $ (\B[3]~input_o )) ) + ( \_~11  ) + ( \_~10  ))
// \_~15  = SHARE((\A[3]~input_o  & (!\op[0]~input_o  $ (!\B[3]~input_o ))))

	.dataa(gnd),
	.datab(!\op[0]~input_o ),
	.datac(!\A[3]~input_o ),
	.datad(!\B[3]~input_o ),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(\_~10 ),
	.sharein(\_~11 ),
	.combout(),
	.sumout(\_~13_sumout ),
	.cout(\_~14 ),
	.shareout(\_~15 ));
// synopsys translate_off
defparam \_~13 .extended_lut = "off";
defparam \_~13 .lut_mask = 64'h0000030C00003CC3;
defparam \_~13 .shared_arith = "on";
// synopsys translate_on

// Location: LABCELL_X18_Y4_N42
cyclonev_lcell_comb \_~17 (
// Equation(s):
// \_~17_sumout  = SUM(( GND ) + ( \_~15  ) + ( \_~14  ))

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(\_~14 ),
	.sharein(\_~15 ),
	.combout(),
	.sumout(\_~17_sumout ),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \_~17 .extended_lut = "off";
defparam \_~17 .lut_mask = 64'h0000000000000000;
defparam \_~17 .shared_arith = "on";
// synopsys translate_on

// Location: LABCELL_X18_Y4_N0
cyclonev_lcell_comb \OUT_CIN~0 (
// Equation(s):
// \OUT_CIN~0_combout  = ( \B[3]~input_o  & ( \op[0]~input_o  & ( !\_~13_sumout  $ (!\A[3]~input_o ) ) ) ) # ( !\B[3]~input_o  & ( \op[0]~input_o  & ( !\_~13_sumout  $ (\A[3]~input_o ) ) ) ) # ( \B[3]~input_o  & ( !\op[0]~input_o  & ( !\_~13_sumout  $ 
// (\A[3]~input_o ) ) ) ) # ( !\B[3]~input_o  & ( !\op[0]~input_o  & ( !\_~13_sumout  $ (!\A[3]~input_o ) ) ) )

	.dataa(gnd),
	.datab(!\_~13_sumout ),
	.datac(gnd),
	.datad(!\A[3]~input_o ),
	.datae(!\B[3]~input_o ),
	.dataf(!\op[0]~input_o ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\OUT_CIN~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \OUT_CIN~0 .extended_lut = "off";
defparam \OUT_CIN~0 .lut_mask = 64'h33CCCC33CC3333CC;
defparam \OUT_CIN~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y27_N0
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\~QUARTUS_CREATED_GND~I_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
// synopsys translate_on

endmodule