Flow report for seven_seg Tue Sep 15 16:10:32 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Flow Summary 3. Flow Settings 4. Flow Non-Default Global Settings 5. Flow Elapsed Time 6. Flow OS Summary 7. Flow Log 8. Flow Messages 9. Flow Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2025 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus Prime License Agreement, the Altera IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the Altera Software License Subscription Agreements on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+-------------------------------------------------+ ; Flow Status ; Successful - Tue Sep 15 16:10:32 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; seven_seg ; ; Top-level Entity Name ; seven_seg ; ; Family ; Cyclone V ; ; Device ; 5CGXFC5C6F27C7 ; ; Timing Models ; Final ; ; Logic utilization (in ALMs) ; 5 / 29,080 ( < 1 % ) ; ; Total registers ; 0 ; ; Total pins ; 13 / 364 ( 4 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; ; Total DSP Blocks ; 0 / 150 ( 0 % ) ; ; Total HSSI RX PCSs ; 0 / 6 ( 0 % ) ; ; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % ) ; ; Total HSSI TX PCSs ; 0 / 6 ( 0 % ) ; ; Total HSSI PMA TX Serializers ; 0 / 6 ( 0 % ) ; ; Total PLLs ; 0 / 12 ( 0 % ) ; ; Total DLLs ; 0 / 4 ( 0 % ) ; +---------------------------------+-------------------------------------------------+ +-----------------------------------------+ ; Flow Settings ; +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ ; Start date & time ; 09/15/2026 16:09:34 ; ; Main task ; Compilation ; ; Revision Name ; seven_seg ; +-------------------+---------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------+ ; Flow Non-Default Global Settings ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; COMPILER_SIGNATURE_ID ; 268883478169649.178945257408043 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ; ; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ; ; EDA_SIMULATION_TOOL ; Questa Altera FPGA (SystemVerilog) ; ; -- ; -- ; ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; ; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; ; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Flow Elapsed Time ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:24 ; ; Fitter ; 00:00:28 ; 1.0 ; 1384 MB ; 00:00:40 ; ; Assembler ; 00:00:05 ; 1.0 ; 521 MB ; 00:00:05 ; ; Timing Analyzer ; 00:00:05 ; 1.0 ; 788 MB ; 00:00:06 ; ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ; ; Total ; 00:00:50 ; -- ; -- ; 00:01:16 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------------------------------------------------------------------+ ; Flow OS Summary ; +----------------------+---------------------+------------+------------+----------------+ ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; +----------------------+---------------------+------------+------------+----------------+ ; Analysis & Synthesis ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; ; Fitter ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; ; Assembler ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; ; Timing Analyzer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; ; EDA Netlist Writer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +----------------------+---------------------+------------+------------+----------------+ ------------ ; Flow Log ; ------------ quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg quartus_sta q1 -c seven_seg quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg