{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1792037050413 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792037050419 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 15 15:04:10 2026 " "Processing started: Thu Oct 15 15:04:10 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792037050419 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037050419 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037050420 ""}
{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1792037050731 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 14 14 " "Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" {  } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" {  } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" {  } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" {  } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" {  } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" {  } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" {  } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" {  } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" {  } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "11 sign_extender " "Found entity 11: sign_extender" {  } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg " "Found entity 12: seven_seg" {  } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "13 seven_seg_4digit " "Found entity 13: seven_seg_4digit" {  } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""} { "Info" "ISGN_ENTITY_NAME" "14 assignment2 " "Found entity 14: assignment2" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792037059808 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037059808 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1792037059945 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 assignment2.sv(100) " "Verilog HDL assignment warning at assignment2.sv(100): truncated value with size 32 to match size of target (10)" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 100 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792037059951 "|assignment2"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "flags\[2\] 0 assignment2.sv(55) " "Net \"flags\[2\]\" at assignment2.sv(55) has no driver or initial value, using a default initial value '0'" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 55 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792037059954 "|assignment2"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" {  } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 62 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037059972 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" {  } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 64 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037059977 ""}
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } }  } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1792037059990 "|assignment2|rom:ROM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792037060027 "|assignment2|rom:ROM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792037060027 "|assignment2|rom:ROM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792037060027 "|assignment2|rom:ROM"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram ram:RAM " "Elaborating entity \"ram\" for hierarchy \"ram:RAM\"" {  } { { "../../modules/assignment2.sv" "RAM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 67 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037060031 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 ram.sv(23) " "Verilog HDL assignment warning at ram.sv(23): truncated value with size 32 to match size of target (8)" {  } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792037060808 "|assignment2|ram:RAM"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" {  } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 69 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037060822 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" {  } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 76 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037060825 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" {  } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 85 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037060828 ""}
{ "Warning" "WVRFX_VERI_2116_UNCONVERTED" "regs register_file.sv(14) " "Verilog HDL warning at register_file.sv(14): initial value for variable regs should be constant" {  } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 14 0 0 } }  } 0 10855 "Verilog HDL warning at %2!s!: initial value for variable %1!s! should be constant" 0 0 "Analysis & Synthesis" 0 -1 1792037060829 "|assignment2|register_file:REGS"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_extender sign_extender:SIGNEXT " "Elaborating entity \"sign_extender\" for hierarchy \"sign_extender:SIGNEXT\"" {  } { { "../../modules/assignment2.sv" "SIGNEXT" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 88 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037060943 ""}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT" "sign_extender.sv(11) " "Verilog HDL unsupported feature error at sign_extender.sv(11): Procedural Continuous Assignment to register is not supported" {  } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 11 0 0 } }  } 0 10043 "Verilog HDL unsupported feature error at %1!s!: Procedural Continuous Assignment to register is not supported" 0 0 "Analysis & Synthesis" 0 -1 1792037060943 ""}
{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "sign_extender:SIGNEXT " "Can't elaborate user hierarchy \"sign_extender:SIGNEXT\"" {  } { { "../../modules/assignment2.sv" "SIGNEXT" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 88 0 0 } }  } 0 12152 "Can't elaborate user hierarchy \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792037060943 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 8 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 8 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "412 " "Peak virtual memory: 412 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792037061004 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Oct 15 15:04:21 2026 " "Processing ended: Thu Oct 15 15:04:21 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792037061004 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1792037061004 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1792037061004 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792037061004 ""}