module RAM #(addrwidth=9, datawidth=5)(
    input logic [0:0] clk,
    input logic [2**addrwidth-1:0] addr,
    input logic [0:0] we,
    input logic [2**datawidth-1:0] data_in,
    output logic [2**datawidth-1:0] data_out
);

    logic [7:0] mem[(2**(addrwidth+datawidth-3))-1:0];

    // NOTE: Possible issue with assignments still pending by end of initial block
    initial begin
        for (integer ADDR = 0; ADDR < 2**(addrwidth+datawidth-3); ++ADDR) begin
            mem[ADDR] <= 8'b0;
        end
    end

    always_ff(@posedge clk) begin
        if (we) begin
            mem[addr] <= data_in;
        end
    end
    assign data_out = mem[addr];

endmodule;