// Copyright (C) 2025  Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Altera and sold by Altera or its authorized distributors.  Please
// refer to the Altera Software License Subscription Agreements 
// on the Quartus Prime software download page.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"

// DATE "09/15/2026 10:20:23"

// 
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
// 

// 
// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only
// 

`timescale 1 ps/ 1 ps

module instruction_classifier (
	op,
	R,
	B1,
	J,
	B2,
	I,
	F,
	M);
input 	logic [5:0] op ;
output 	logic [0:0] R ;
output 	logic [0:0] B1 ;
output 	logic [0:0] J ;
output 	logic [0:0] B2 ;
output 	logic [0:0] I ;
output 	logic [0:0] F ;
output 	logic [0:0] M ;

// Design Ports Information
// R[0]	=>  Location: PIN_W10,	 I/O Standard: 2.5 V,	 Current Strength: Default
// B1[0]	=>  Location: PIN_AC10,	 I/O Standard: 2.5 V,	 Current Strength: Default
// J[0]	=>  Location: PIN_T12,	 I/O Standard: 2.5 V,	 Current Strength: Default
// B2[0]	=>  Location: PIN_T13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I[0]	=>  Location: PIN_R11,	 I/O Standard: 2.5 V,	 Current Strength: Default
// F[0]	=>  Location: PIN_Y10,	 I/O Standard: 2.5 V,	 Current Strength: Default
// M[0]	=>  Location: PIN_T11,	 I/O Standard: 2.5 V,	 Current Strength: Default
// op[0]	=>  Location: PIN_AB12,	 I/O Standard: 2.5 V,	 Current Strength: Default
// op[1]	=>  Location: PIN_AB11,	 I/O Standard: 2.5 V,	 Current Strength: Default
// op[2]	=>  Location: PIN_T9,	 I/O Standard: 2.5 V,	 Current Strength: Default
// op[3]	=>  Location: PIN_AC8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// op[4]	=>  Location: PIN_AC9,	 I/O Standard: 2.5 V,	 Current Strength: Default
// op[5]	=>  Location: PIN_AB10,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \~QUARTUS_CREATED_GND~I_combout ;
wire \op[5]~input_o ;
wire \op[0]~input_o ;
wire \op[2]~input_o ;
wire \op[1]~input_o ;
wire \op[4]~input_o ;
wire \op[3]~input_o ;
wire \Equal0~0_combout ;
wire \Equal1~0_combout ;
wire \Equal2~0_combout ;
wire \Equal3~0_combout ;
wire \Equal4~0_combout ;
wire \Equal5~0_combout ;


// Location: IOOBUF_X15_Y0_N36
cyclonev_io_obuf \R[0]~output (
	.i(\Equal0~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(R[0]),
	.obar());
// synopsys translate_off
defparam \R[0]~output .bus_hold = "false";
defparam \R[0]~output .open_drain_output = "false";
defparam \R[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X12_Y0_N53
cyclonev_io_obuf \B1[0]~output (
	.i(\Equal1~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(B1[0]),
	.obar());
// synopsys translate_off
defparam \B1[0]~output .bus_hold = "false";
defparam \B1[0]~output .open_drain_output = "false";
defparam \B1[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X15_Y0_N19
cyclonev_io_obuf \J[0]~output (
	.i(\Equal2~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(J[0]),
	.obar());
// synopsys translate_off
defparam \J[0]~output .bus_hold = "false";
defparam \J[0]~output .open_drain_output = "false";
defparam \J[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X15_Y0_N2
cyclonev_io_obuf \B2[0]~output (
	.i(\Equal3~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(B2[0]),
	.obar());
// synopsys translate_off
defparam \B2[0]~output .bus_hold = "false";
defparam \B2[0]~output .open_drain_output = "false";
defparam \B2[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X12_Y0_N2
cyclonev_io_obuf \I[0]~output (
	.i(\Equal4~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(I[0]),
	.obar());
// synopsys translate_off
defparam \I[0]~output .bus_hold = "false";
defparam \I[0]~output .open_drain_output = "false";
defparam \I[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X15_Y0_N53
cyclonev_io_obuf \F[0]~output (
	.i(\Equal5~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(F[0]),
	.obar());
// synopsys translate_off
defparam \F[0]~output .bus_hold = "false";
defparam \F[0]~output .open_drain_output = "false";
defparam \F[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X12_Y0_N19
cyclonev_io_obuf \M[0]~output (
	.i(\op[5]~input_o ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(M[0]),
	.obar());
// synopsys translate_off
defparam \M[0]~output .bus_hold = "false";
defparam \M[0]~output .open_drain_output = "false";
defparam \M[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOIBUF_X12_Y0_N35
cyclonev_io_ibuf \op[5]~input (
	.i(op[5]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\op[5]~input_o ));
// synopsys translate_off
defparam \op[5]~input .bus_hold = "false";
defparam \op[5]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X14_Y0_N1
cyclonev_io_ibuf \op[0]~input (
	.i(op[0]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\op[0]~input_o ));
// synopsys translate_off
defparam \op[0]~input .bus_hold = "false";
defparam \op[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X10_Y0_N75
cyclonev_io_ibuf \op[2]~input (
	.i(op[2]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\op[2]~input_o ));
// synopsys translate_off
defparam \op[2]~input .bus_hold = "false";
defparam \op[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X14_Y0_N18
cyclonev_io_ibuf \op[1]~input (
	.i(op[1]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\op[1]~input_o ));
// synopsys translate_off
defparam \op[1]~input .bus_hold = "false";
defparam \op[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X14_Y0_N35
cyclonev_io_ibuf \op[4]~input (
	.i(op[4]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\op[4]~input_o ));
// synopsys translate_off
defparam \op[4]~input .bus_hold = "false";
defparam \op[4]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X14_Y0_N52
cyclonev_io_ibuf \op[3]~input (
	.i(op[3]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\op[3]~input_o ));
// synopsys translate_off
defparam \op[3]~input .bus_hold = "false";
defparam \op[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: MLABCELL_X14_Y1_N30
cyclonev_lcell_comb \Equal0~0 (
// Equation(s):
// \Equal0~0_combout  = ( !\op[4]~input_o  & ( !\op[3]~input_o  & ( (!\op[5]~input_o  & (!\op[0]~input_o  & (!\op[2]~input_o  & !\op[1]~input_o ))) ) ) )

	.dataa(!\op[5]~input_o ),
	.datab(!\op[0]~input_o ),
	.datac(!\op[2]~input_o ),
	.datad(!\op[1]~input_o ),
	.datae(!\op[4]~input_o ),
	.dataf(!\op[3]~input_o ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\Equal0~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \Equal0~0 .extended_lut = "off";
defparam \Equal0~0 .lut_mask = 64'h8000000000000000;
defparam \Equal0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y1_N6
cyclonev_lcell_comb \Equal1~0 (
// Equation(s):
// \Equal1~0_combout  = ( !\op[4]~input_o  & ( !\op[3]~input_o  & ( (!\op[5]~input_o  & (\op[0]~input_o  & (!\op[2]~input_o  & !\op[1]~input_o ))) ) ) )

	.dataa(!\op[5]~input_o ),
	.datab(!\op[0]~input_o ),
	.datac(!\op[2]~input_o ),
	.datad(!\op[1]~input_o ),
	.datae(!\op[4]~input_o ),
	.dataf(!\op[3]~input_o ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\Equal1~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \Equal1~0 .extended_lut = "off";
defparam \Equal1~0 .lut_mask = 64'h2000000000000000;
defparam \Equal1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y1_N42
cyclonev_lcell_comb \Equal2~0 (
// Equation(s):
// \Equal2~0_combout  = ( !\op[4]~input_o  & ( !\op[3]~input_o  & ( (!\op[5]~input_o  & (\op[1]~input_o  & !\op[2]~input_o )) ) ) )

	.dataa(!\op[5]~input_o ),
	.datab(!\op[1]~input_o ),
	.datac(!\op[2]~input_o ),
	.datad(gnd),
	.datae(!\op[4]~input_o ),
	.dataf(!\op[3]~input_o ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\Equal2~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \Equal2~0 .extended_lut = "off";
defparam \Equal2~0 .lut_mask = 64'h2020000000000000;
defparam \Equal2~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y1_N51
cyclonev_lcell_comb \Equal3~0 (
// Equation(s):
// \Equal3~0_combout  = ( !\op[4]~input_o  & ( !\op[3]~input_o  & ( (\op[2]~input_o  & !\op[5]~input_o ) ) ) )

	.dataa(!\op[2]~input_o ),
	.datab(gnd),
	.datac(gnd),
	.datad(!\op[5]~input_o ),
	.datae(!\op[4]~input_o ),
	.dataf(!\op[3]~input_o ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\Equal3~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \Equal3~0 .extended_lut = "off";
defparam \Equal3~0 .lut_mask = 64'h5500000000000000;
defparam \Equal3~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y1_N24
cyclonev_lcell_comb \Equal4~0 (
// Equation(s):
// \Equal4~0_combout  = ( !\op[4]~input_o  & ( \op[3]~input_o  & ( !\op[5]~input_o  ) ) )

	.dataa(gnd),
	.datab(gnd),
	.datac(!\op[5]~input_o ),
	.datad(gnd),
	.datae(!\op[4]~input_o ),
	.dataf(!\op[3]~input_o ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\Equal4~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \Equal4~0 .extended_lut = "off";
defparam \Equal4~0 .lut_mask = 64'h00000000F0F00000;
defparam \Equal4~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y1_N3
cyclonev_lcell_comb \Equal5~0 (
// Equation(s):
// \Equal5~0_combout  = ( \op[4]~input_o  & ( !\op[5]~input_o  ) )

	.dataa(!\op[5]~input_o ),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(!\op[4]~input_o ),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\Equal5~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \Equal5~0 .extended_lut = "off";
defparam \Equal5~0 .lut_mask = 64'h0000AAAA0000AAAA;
defparam \Equal5~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y25_N3
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\~QUARTUS_CREATED_GND~I_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
// synopsys translate_on

endmodule