`ifndef CONTROL_UNIT_H
`define CONTROL_UNIT_H
`include "instruction_classifier.sv"

module control_unit (
    input logic [5:0] op, input logic [5:0] func,
    output logic [0:0] M2R,     //  Enables writing data stored in memory at the address (rs/A)+(ALU_SRC ? imm : rt/B) into rd
    output logic [0:0] M2W,     //  Enable writing data stored in rt/B into memory at the address (rs/A)+(ALU_SRC ? imm : rt/B)
    output logic [0:0] B,       //  AND'ed with flags to determine if branch is permitted
    output logic [3:0] ALU_FN,  //  Controls what function the ALU is to perform
    output logic [0:0] ALU_SRC, //  Controls whether to use the rt/B register read port or 16-bit immediate 
    output logic [0:0] RDST,    //  Controls where to look in the instruction encoding for the register write address
    output logic [0:0] RW       //  Enable register write port
);
    logic [0:0] TYPE_R;
    logic [0:0] TYPE_B1;
    logic [0:0] TYPE_J;
    logic [0:0] TYPE_B2;
    logic [0:0] TYPE_I;
    logic [0:0] TYPE_F;
    logic [0:0] TYPE_M;

    instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);

    always_comb begin
        M2R = TYPE_M & ~((op & 6'b001000) >> 3);
        M2W = TYPE_M & ((op & 6'b001000) >> 3);
        B = TYPE_B1 | TYPE_B2 | TYPE_J;
        ALU_FN = (func & {(4){TYPE_R}}) | ( {2'b00, (op & 6'b000011)} & {(4){TYPE_I}}) | (4'b0010 & {4{TYPE_B1 | TYPE_B2}});
        ALU_SRC = TYPE_I | TYPE_M;
        RDST = TYPE_R;  // Imm ops store back into rt
        RW = TYPE_R | TYPE_I | M2R;
    end

endmodule
`endif