`ifndef ASS_2_SV
`define ASS_2_SV

`include "rom.sv"
`include "ram.sv"
`include "register_file.sv"
`include "instruction_counter.sv"
`include "control_unit.sv"
`include "alu.sv"
`include "shifter.sv"
`include "sign_extender.sv"
`include "seven_seg_4digit.sv"


module assignment2 #(width=5, romsz=10) (
	input logic [0:0] clk
`ifdef QUARTUS_SYNTH
    ,
	input logic [4:0] HID_Register,
	input logic [0:0] HID_PC,
	input logic [0:0] HID_Hi_Low,
	
	output logic[7:0] out_seg_0,
	output logic[7:0] out_seg_1,
	output logic[7:0] out_seg_2,
	output logic[7:0] out_seg_3
`endif
	);
	// Intermediate for displaying high / low of PC or Register
	logic[15:0] PC_Reg_Display;
	
	// Program / Instruction Counter Intermediates
	logic [romsz-1:0] pc_addr;
	logic [romsz-1:0] pc_addr_write;
	logic [0:0] pc_we;
	logic [2**width-1:0] instruction;
	
	// Instruction Classifier Intermediates
	logic [0:0] M2R;
	logic [0:0] M2W;
    logic [0:0] B;
    logic [3:0] ALU_FN;
	logic [0:0] ALU_SRC;
    logic [0:0] RDST;
	logic [0:0] RW;
		
	// Register File intermediates
	logic [2:0] flags;
	logic [2**width-1:0] rs;
	logic [2**width-1:0] rt;
	logic [2**width-1:0] rd;
	logic [0:0] rd_we;
	logic [31:0] regs_out [32];

    // ALU intermediates
	logic [2**width-1:0] rd_alu;
	logic [2**width-1:0] rt_alu;
	
	instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
	
	rom #(romsz, 2**width) ROM (pc_addr, instruction);

	logic [2**width-1:0] rd_mem;
	ram #(width) RAM (clk, rd_alu, M2W, rt, rd_mem);
	
	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
		M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
	);


	register_file #(width, 5) REGS (
		clk, rd_we, 
		instruction[20:16], rd,
		(RDST) ? instruction[15:11] : instruction[20:16], rt,
		instruction[25:21], rs, 
		regs_out
   );
    // Always use sign-extension
    logic [2**width-1:0] rt_imm;
    sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
    // TODO:
    //  - ALU srcB
    //  - PCBranch (rel jump of 4-byte words)


	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]);
    assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);

	assign pc_we = B & flags[2];
	assign pc_addr_write = (rt_imm << 2) + pc_addr;
	assign rd_we = RW;
	assign rd = (M2R) ? rd_alu : rd_mem;



	// Temporary Test output
	// assign PC_Reg_Display = 16'hC342;

   assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
	
	seven_seg_4digit display (
		.num(PC_Reg_Display),
		.segments0(out_seg_0),
		.segments1(out_seg_1),
		.segments2(out_seg_2),
		.segments3(out_seg_3)
	);

endmodule
`endif