// Copyright (C) 2025  Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Altera and sold by Altera or its authorized distributors.  Please
// refer to the Altera Software License Subscription Agreements 
// on the Quartus Prime software download page.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"

// DATE "09/09/2026 14:23:06"

// 
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
// 

// 
// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only
// 

`timescale 1 ps/ 1 ps

module alu (
	op,
	A,
	B,
	OUT_1,
	flags);
input 	logic [3:0] op ;
input 	logic [3:0] A ;
input 	logic [3:0] B ;
output 	logic [3:0] OUT_1 ;
output 	logic flags [1:0];

// Design Ports Information
// op[0]	=>  Location: PIN_H9,	 I/O Standard: 2.5 V,	 Current Strength: Default
// op[1]	=>  Location: PIN_B24,	 I/O Standard: 2.5 V,	 Current Strength: Default
// op[2]	=>  Location: PIN_K24,	 I/O Standard: 2.5 V,	 Current Strength: Default
// op[3]	=>  Location: PIN_V25,	 I/O Standard: 2.5 V,	 Current Strength: Default
// A[0]	=>  Location: PIN_U22,	 I/O Standard: 2.5 V,	 Current Strength: Default
// A[1]	=>  Location: PIN_AF21,	 I/O Standard: 2.5 V,	 Current Strength: Default
// A[2]	=>  Location: PIN_AB17,	 I/O Standard: 2.5 V,	 Current Strength: Default
// A[3]	=>  Location: PIN_AA18,	 I/O Standard: 2.5 V,	 Current Strength: Default
// B[0]	=>  Location: PIN_C19,	 I/O Standard: 2.5 V,	 Current Strength: Default
// B[1]	=>  Location: PIN_T13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// B[2]	=>  Location: PIN_B20,	 I/O Standard: 2.5 V,	 Current Strength: Default
// B[3]	=>  Location: PIN_E26,	 I/O Standard: 2.5 V,	 Current Strength: Default
// OUT_1[0]	=>  Location: PIN_A5,	 I/O Standard: 2.5 V,	 Current Strength: Default
// OUT_1[1]	=>  Location: PIN_AA7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// OUT_1[2]	=>  Location: PIN_AF16,	 I/O Standard: 2.5 V,	 Current Strength: Default
// OUT_1[3]	=>  Location: PIN_E11,	 I/O Standard: 2.5 V,	 Current Strength: Default
// flags[0]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
// flags[1]	=>  Location: PIN_W25,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \op[0]~input_o ;
wire \op[1]~input_o ;
wire \op[2]~input_o ;
wire \op[3]~input_o ;
wire \A[0]~input_o ;
wire \A[1]~input_o ;
wire \A[2]~input_o ;
wire \A[3]~input_o ;
wire \B[0]~input_o ;
wire \B[1]~input_o ;
wire \B[2]~input_o ;
wire \B[3]~input_o ;
wire \~QUARTUS_CREATED_GND~I_combout ;


// Location: IOOBUF_X21_Y61_N36
cyclonev_io_obuf \OUT_1[0]~output (
	.i(gnd),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_1[0]),
	.obar());
// synopsys translate_off
defparam \OUT_1[0]~output .bus_hold = "false";
defparam \OUT_1[0]~output .open_drain_output = "false";
defparam \OUT_1[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X6_Y0_N53
cyclonev_io_obuf \OUT_1[1]~output (
	.i(gnd),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_1[1]),
	.obar());
// synopsys translate_off
defparam \OUT_1[1]~output .bus_hold = "false";
defparam \OUT_1[1]~output .open_drain_output = "false";
defparam \OUT_1[1]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X59_Y0_N19
cyclonev_io_obuf \OUT_1[2]~output (
	.i(gnd),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_1[2]),
	.obar());
// synopsys translate_off
defparam \OUT_1[2]~output .bus_hold = "false";
defparam \OUT_1[2]~output .open_drain_output = "false";
defparam \OUT_1[2]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X40_Y61_N93
cyclonev_io_obuf \OUT_1[3]~output (
	.i(gnd),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_1[3]),
	.obar());
// synopsys translate_off
defparam \OUT_1[3]~output .bus_hold = "false";
defparam \OUT_1[3]~output .open_drain_output = "false";
defparam \OUT_1[3]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X36_Y61_N19
cyclonev_io_obuf \flags[0]~output (
	.i(gnd),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(flags[0]),
	.obar());
// synopsys translate_off
defparam \flags[0]~output .bus_hold = "false";
defparam \flags[0]~output .open_drain_output = "false";
defparam \flags[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X68_Y26_N39
cyclonev_io_obuf \flags[1]~output (
	.i(gnd),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(flags[1]),
	.obar());
// synopsys translate_off
defparam \flags[1]~output .bus_hold = "false";
defparam \flags[1]~output .open_drain_output = "false";
defparam \flags[1]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOIBUF_X19_Y61_N18
cyclonev_io_ibuf \op[0]~input (
	.i(op[0]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\op[0]~input_o ));
// synopsys translate_off
defparam \op[0]~input .bus_hold = "false";
defparam \op[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X65_Y61_N1
cyclonev_io_ibuf \op[1]~input (
	.i(op[1]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\op[1]~input_o ));
// synopsys translate_off
defparam \op[1]~input .bus_hold = "false";
defparam \op[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X68_Y41_N4
cyclonev_io_ibuf \op[2]~input (
	.i(op[2]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\op[2]~input_o ));
// synopsys translate_off
defparam \op[2]~input .bus_hold = "false";
defparam \op[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X68_Y19_N55
cyclonev_io_ibuf \op[3]~input (
	.i(op[3]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\op[3]~input_o ));
// synopsys translate_off
defparam \op[3]~input .bus_hold = "false";
defparam \op[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X68_Y12_N21
cyclonev_io_ibuf \A[0]~input (
	.i(A[0]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\A[0]~input_o ));
// synopsys translate_off
defparam \A[0]~input .bus_hold = "false";
defparam \A[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X51_Y0_N35
cyclonev_io_ibuf \A[1]~input (
	.i(A[1]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\A[1]~input_o ));
// synopsys translate_off
defparam \A[1]~input .bus_hold = "false";
defparam \A[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X51_Y0_N1
cyclonev_io_ibuf \A[2]~input (
	.i(A[2]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\A[2]~input_o ));
// synopsys translate_off
defparam \A[2]~input .bus_hold = "false";
defparam \A[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X62_Y0_N58
cyclonev_io_ibuf \A[3]~input (
	.i(A[3]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\A[3]~input_o ));
// synopsys translate_off
defparam \A[3]~input .bus_hold = "false";
defparam \A[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X59_Y61_N35
cyclonev_io_ibuf \B[0]~input (
	.i(B[0]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\B[0]~input_o ));
// synopsys translate_off
defparam \B[0]~input .bus_hold = "false";
defparam \B[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X15_Y0_N1
cyclonev_io_ibuf \B[1]~input (
	.i(B[1]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\B[1]~input_o ));
// synopsys translate_off
defparam \B[1]~input .bus_hold = "false";
defparam \B[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X62_Y61_N92
cyclonev_io_ibuf \B[2]~input (
	.i(B[2]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\B[2]~input_o ));
// synopsys translate_off
defparam \B[2]~input .bus_hold = "false";
defparam \B[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X68_Y37_N55
cyclonev_io_ibuf \B[3]~input (
	.i(B[3]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\B[3]~input_o ));
// synopsys translate_off
defparam \B[3]~input .bus_hold = "false";
defparam \B[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LABCELL_X46_Y55_N0
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\~QUARTUS_CREATED_GND~I_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
// synopsys translate_on

endmodule