module gatereg #(width, ndelay=1)(
    input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] en,
    input logic [2**width-1:0] in, output logic [2**width-1:0] out
);
    logic [2**width-1:0] hold_value[ndelay];

    assign out = hold_value[ndelay-1];
    always_ff @( posedge clk ) begin
        if (rst) begin
            for (integer i = 0; i < ndelay; ++i) begin
                hold_value[i] <= {(2**width){1'b0}};
            end
        end else if (en) begin
            hold_value[0] <= in;
            for (integer i = 1; i < ndelay; ++i) begin
                hold_value[i] <= hold_value[i-1];
            end
        end
    end

endmodule