# Loading project Assignment_2
# Compile of alu.sv was successful.
# Compile of alu_tb.sv was successful.
# Compile of assignment2.sv was successful.
# Compile of asu.sv was successful.
# Compile of asu_tb.sv was successful.
# Compile of ByteIM.sv was successful.
# Compile of control_unit.sv was successful.
# Compile of instruction_classifier.sv was successful.
# Compile of instruction_classifier_tb.sv was successful.
# Compile of instruction_counter.sv was successful.
# Compile of lu.sv was successful.
# Compile of lu_tb.sv was successful.
# Compile of mips.sv was successful.
# Compile of ram.sv was successful.
# Compile of register_file.sv was successful.
# Compile of rom.sv was successful.
# Compile of seven_seg.sv was successful.
# Compile of seven_seg_4digit.sv was successful.
# Compile of seven_seg_tb.sv was successful.
# Compile of shifter.sv was successful.
# Compile of shifter_tb.sv was successful.
# Compile of sign_extender.sv was successful.
# 22 compiles, 0 failed with no errors.
vsim work.mips_tb
# vsim work.mips_tb 
# Start time: 12:45:51 on Oct 16,2026
# Loading sv_std.std
# Loading work.mips_tb
# Loading work.assignment2
# Loading work.instruction_counter
# Loading work.rom
# Loading work.ram
# Loading work.control_unit
# Loading work.instruction_classifier
# Loading work.register_file
# Loading work.sign_extender
# Loading work.alu
# Loading work.asu
# Loading work.lu
# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5).
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61
# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8).
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9).
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
add wave -position end  sim:/mips_tb/rst
add wave -position end  sim:/mips_tb/clk
run
# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18.    : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/ROM
run
force -freeze sim:/mips_tb/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/mips_tb/clk 1 0, 0 {10 ns} -r 20
run
quit -sim
# End time: 12:47:55 on Oct 16,2026, Elapsed time: 0:02:04
# Errors: 0, Warnings: 7
vsim work.mips_tb
# vsim work.mips_tb 
# Start time: 12:47:56 on Oct 16,2026
# Loading sv_std.std
# Loading work.mips_tb
# Loading work.assignment2
# Loading work.instruction_counter
# Loading work.rom
# Loading work.ram
# Loading work.control_unit
# Loading work.instruction_classifier
# Loading work.register_file
# Loading work.sign_extender
# Loading work.alu
# Loading work.asu
# Loading work.lu
# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5).
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61
# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8).
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9).
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
add wave -position end  sim:/mips_tb/clk
add wave -position end  sim:/mips_tb/rst
add wave -position end  sim:/mips_tb/num_errors
force -freeze sim:/mips_tb/rst 1 0 -cancel 20
force -freeze sim:/mips_tb/clk 1 0, 0 {10 ns} -r 20
force -freeze sim:/mips_tb/clk 0 0, 1 {50 ns} -r 100
run
# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18.    : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/ROM
add wave -position end  sim:/mips_tb/CPU/regs_out
run
quit -sim
# End time: 12:50:34 on Oct 16,2026, Elapsed time: 0:02:38
# Errors: 0, Warnings: 6
vsim work.mips_tb
# vsim work.mips_tb 
# Start time: 12:50:36 on Oct 16,2026
# Loading sv_std.std
# Loading work.mips_tb
# Loading work.assignment2
# Loading work.instruction_counter
# Loading work.rom
# Loading work.ram
# Loading work.control_unit
# Loading work.instruction_classifier
# Loading work.register_file
# Loading work.sign_extender
# Loading work.alu
# Loading work.asu
# Loading work.lu
# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5).
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61
# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8).
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9).
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
add wave -position end  sim:/mips_tb/clk
add wave -position end  sim:/mips_tb/rst
add wave -position end  sim:/mips_tb/num_errors
add wave -position end  sim:/mips_tb/CPU/regs_out
run
# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18.    : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
#    Time: 0 ns  Iteration: 0  Instance: /mips_tb/CPU/ROM
# End time: 12:55:34 on Oct 16,2026, Elapsed time: 0:04:58
# Errors: 0, Warnings: 6