# Loading project Assignment_1_Q2 # reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini # Loading project Assignment_2 # Compile of alu.sv was successful with warnings. # Compile of alu_tb.sv was successful with warnings. # Compile of assignment2.sv failed with 3 errors. # Compile of asu.sv was successful. # Compile of asu_tb.sv was successful. # Compile of ByteIM.sv failed with 1 errors. # Compile of control_unit.sv was successful. # Compile of instruction_classifier.sv was successful. # Compile of instruction_classifier_tb.sv was successful. # Compile of instruction_counter.sv was successful. # Compile of lu.sv was successful. # Compile of lu_tb.sv was successful. # Compile of mips.sv failed with 3 errors. # Compile of ram.sv was successful. # Compile of register_file.sv was successful. # Compile of rom.sv was successful. # Compile of seven_seg.sv was successful. # Compile of seven_seg_4digit.sv was successful. # Compile of seven_seg_tb.sv was successful. # Compile of shifter.sv was successful. # Compile of shifter_tb.sv was successful. # Compile of sign_extender.sv was successful. # Compile of tests.sv failed with 6 errors. # 23 compiles, 4 failed with 13 errors. # Compile of assignment2.sv failed with 3 errors. # Compile of assignment2.sv failed with 1 errors. # Compile of assignment2.sv failed with 1 errors. # Compile of assignment2.sv was successful with warnings. # Compile of mips.sv was successful with warnings. # Compile of ByteIM.sv failed with 1 errors. # Compile of ByteIM.sv was successful. # Compile of alu.sv was successful with warnings. # Compile of alu_tb.sv was successful with warnings. # Compile of assignment2.sv was successful with warnings. # Compile of asu.sv was successful. # Compile of asu_tb.sv was successful. # Compile of ByteIM.sv was successful. # Compile of control_unit.sv was successful. # Compile of instruction_classifier.sv was successful. # Compile of instruction_classifier_tb.sv was successful. # Compile of instruction_counter.sv was successful. # Compile of lu.sv was successful. # Compile of lu_tb.sv was successful. # Compile of mips.sv was successful with warnings. # Compile of ram.sv was successful. # Compile of register_file.sv was successful. # Compile of rom.sv was successful. # Compile of seven_seg.sv was successful. # Compile of seven_seg_4digit.sv was successful. # Compile of seven_seg_tb.sv was successful. # Compile of shifter.sv was successful. # Compile of shifter_tb.sv was successful. # Compile of sign_extender.sv was successful. # 22 compiles, 0 failed with no errors. vsim work.mips_tb # vsim work.mips_tb # Start time: 10:28:41 on Oct 16,2026 # Loading sv_std.std # Loading work.mips_tb # Loading work.assignment2 # Loading work.instruction_counter # Loading work.rom # Loading work.ram # Loading work.control_unit # Loading work.instruction_classifier # Loading work.register_file # Loading work.sign_extender # Loading work.alu # Loading work.asu # Loading work.lu # Loading work.seven_seg_4digit # Loading work.seven_seg # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'. Expected 8, found 1. # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15 # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'. # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 # ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61 # ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82 add wave -position end sim:/mips_tb/clk add wave -position end sim:/mips_tb/num_errors add wave -position end sim:/mips_tb/CPU/instruction run # ** Warning: (vsim-7) Failed to open readmem file "./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt" in read mode. # No such file or directory. (errno = ENOENT) : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18) # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ROM # Beginning MIPS tests # Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[8] == 32'd10 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[9] == 32'd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[10] == 32'd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[11] == 32'd14 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[12] == -32'sd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[13] == 32'd10 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[14] == 32'd3 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[16] == 32'd2 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[17] == 32'd15 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[18] == 32'd13 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[19] == -32'sd16 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[20] == 32'd1 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # All MIPS tests passing quit -sim # End time: 10:32:02 on Oct 16,2026, Elapsed time: 0:03:21 # Errors: 0, Warnings: 27 # Compile of alu.sv was successful with warnings. # Compile of alu_tb.sv was successful with warnings. # Compile of assignment2.sv was successful with warnings. # Compile of asu.sv was successful. # Compile of asu_tb.sv was successful. # Compile of ByteIM.sv was successful. # Compile of control_unit.sv was successful. # Compile of instruction_classifier.sv was successful. # Compile of instruction_classifier_tb.sv was successful. # Compile of instruction_counter.sv was successful. # Compile of lu.sv was successful. # Compile of lu_tb.sv was successful. # Compile of mips.sv was successful with warnings. # Compile of ram.sv was successful. # Compile of register_file.sv was successful. # Compile of rom.sv was successful. # Compile of seven_seg.sv was successful. # Compile of seven_seg_4digit.sv was successful. # Compile of seven_seg_tb.sv was successful. # Compile of shifter.sv was successful. # Compile of shifter_tb.sv was successful. # Compile of sign_extender.sv was successful. # 22 compiles, 0 failed with no errors. vsim work.mips_tb # vsim work.mips_tb # Start time: 10:33:32 on Oct 16,2026 # Loading sv_std.std # Loading work.mips_tb # Loading work.assignment2 # Loading work.instruction_counter # Loading work.rom # Loading work.ram # Loading work.control_unit # Loading work.instruction_classifier # Loading work.register_file # Loading work.sign_extender # Loading work.alu # Loading work.asu # Loading work.lu # Loading work.seven_seg_4digit # Loading work.seven_seg # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'. Expected 8, found 1. # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15 # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'. # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 # ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61 # ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82 run # Beginning MIPS tests # Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[8] == 32'd10 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[9] == 32'd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[10] == 32'd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[11] == 32'd14 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[12] == -32'sd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[13] == 32'd10 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[14] == 32'd3 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[16] == 32'd2 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[17] == 32'd15 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[18] == 32'd13 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[19] == -32'sd16 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[20] == 32'd1 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # All MIPS tests passing add wave -position end sim:/mips_tb/clk run -all run quit -sim # End time: 10:42:49 on Oct 16,2026, Elapsed time: 0:09:17 # Errors: 0, Warnings: 14 vsim work.mips_tb # vsim work.mips_tb # Start time: 10:42:57 on Oct 16,2026 # Loading sv_std.std # Loading work.mips_tb # Loading work.assignment2 # Loading work.instruction_counter # Loading work.rom # Loading work.ram # Loading work.control_unit # Loading work.instruction_classifier # Loading work.register_file # Loading work.sign_extender # Loading work.alu # Loading work.asu # Loading work.lu # Loading work.seven_seg_4digit # Loading work.seven_seg # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'. Expected 8, found 1. # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15 # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'. # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 # ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61 # ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82 add wave -position end sim:/mips_tb/clk add wave -position end sim:/mips_tb/CPU/instruction run # Beginning MIPS tests # Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[8] == 32'd10 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[9] == 32'd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[10] == 32'd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[11] == 32'd14 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[12] == -32'sd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[13] == 32'd10 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[14] == 32'd3 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[16] == 32'd2 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[17] == 32'd15 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[18] == 32'd13 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[19] == -32'sd16 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[20] == 32'd1 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # All MIPS tests passing quit -sim # End time: 10:44:19 on Oct 16,2026, Elapsed time: 0:01:22 # Errors: 0, Warnings: 13 vsim work.mips_tb # vsim work.mips_tb # Start time: 10:47:26 on Oct 16,2026 # Loading sv_std.std # Loading work.mips_tb # Loading work.assignment2 # Loading work.instruction_counter # Loading work.rom # Loading work.ram # Loading work.control_unit # Loading work.instruction_classifier # Loading work.register_file # Loading work.sign_extender # Loading work.alu # Loading work.asu # Loading work.lu # Loading work.seven_seg_4digit # Loading work.seven_seg # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'. Expected 8, found 1. # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15 # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'. # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 # ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61 # ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82 add wave -position end sim:/mips_tb/clk force -freeze sim:/mips_tb/clk 1 0, 0 {10 ps} -r 20 run # Beginning MIPS tests # Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[8] == 32'd10 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[9] == 32'd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[10] == 32'd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[11] == 32'd14 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[12] == -32'sd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[13] == 32'd10 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[14] == 32'd3 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[16] == 32'd2 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[17] == 32'd15 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[18] == 32'd13 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[19] == -32'sd16 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[20] == 32'd1 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # All MIPS tests passing add wave -position end sim:/mips_tb/num_errors run run quit -sim # End time: 10:49:38 on Oct 16,2026, Elapsed time: 0:02:12 # Errors: 0, Warnings: 13 vsim work.mips_tb # vsim work.mips_tb # Start time: 10:49:39 on Oct 16,2026 # Loading sv_std.std # Loading work.mips_tb # Loading work.assignment2 # Loading work.instruction_counter # Loading work.rom # Loading work.ram # Loading work.control_unit # Loading work.instruction_classifier # Loading work.register_file # Loading work.sign_extender # Loading work.alu # Loading work.asu # Loading work.lu # Loading work.seven_seg_4digit # Loading work.seven_seg # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'. Expected 8, found 1. # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15 # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'. # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 # ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61 # ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82 add wave -position end sim:/mips_tb/clk add wave -position end sim:/mips_tb/num_errors add wave -position end sim:/mips_tb/CPU/REGS/regs_out add wave -position end sim:/mips_tb/CPU/REGS/regs force -freeze sim:/mips_tb/clk 1 0, 0 {5 ps} -r 10 run # Beginning MIPS tests # Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[8] == 32'd10 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[9] == 32'd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[10] == 32'd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[11] == 32'd14 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[12] == -32'sd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[13] == 32'd10 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[14] == 32'd3 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[16] == 32'd2 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[17] == 32'd15 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[18] == 32'd13 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[19] == -32'sd16 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[20] == 32'd1 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # All MIPS tests passing quit -sim # End time: 10:59:29 on Oct 16,2026, Elapsed time: 0:09:50 # Errors: 0, Warnings: 13 vsim work.ram # vsim work.ram # Start time: 10:59:43 on Oct 16,2026 # Loading sv_std.std # Loading work.ram quit -sim # End time: 10:59:51 on Oct 16,2026, Elapsed time: 0:00:08 # Errors: 0, Warnings: 1 vsim work.mips_tb # vsim work.mips_tb # Start time: 10:59:55 on Oct 16,2026 # Loading sv_std.std # Loading work.mips_tb # Loading work.assignment2 # Loading work.instruction_counter # Loading work.rom # Loading work.ram # Loading work.control_unit # Loading work.instruction_classifier # Loading work.register_file # Loading work.sign_extender # Loading work.alu # Loading work.asu # Loading work.lu # Loading work.seven_seg_4digit # Loading work.seven_seg # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'CPU'. Expected 8, found 1. # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv Line: 15 # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Register'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_PC'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'HID_Hi_Low'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_0'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_1'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_2'. # ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv(15): [TFMPC] - Missing connection for port 'out_seg_3'. # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'W'. The port definition is at: instruction_counter.sv(6). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (10) for port 'addr'. The port definition is at: instruction_counter.sv(7). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/PC File: assignment2.sv Line: 56 # ** Warning: (vsim-3015) [PCDPC] - Port size (512) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 61 # ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (2) for port 'flags'. The port definition is at: alu.sv(11). # Time: 0 ps Iteration: 0 Instance: /mips_tb/CPU/ALU File: assignment2.sv Line: 82 add wave -position end sim:/mips_tb/CPU/instruction add wave -position end sim:/mips_tb/clk add wave -position end sim:/mips_tb/CPU/clk force -freeze sim:/mips_tb/clk 1 0, 0 {25 ps} -r 50 force -freeze sim:/mips_tb/CPU/clk 1 0, 0 {25 ps} -r 50 run # Beginning MIPS tests # Check CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[0] == 32'(N) failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[8] == 32'd10 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[9] == 32'd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[10] == 32'd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[11] == 32'd14 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[12] == -32'sd7 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[13] == 32'd10 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[14] == 32'd3 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[16] == 32'd2 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[17] == 32'd15 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[18] == 32'd13 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[19] == -32'sd16 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # Check CPU.REGS.regs[20] == 32'd1 failed # # t0-t8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # s0-s8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 # # All MIPS tests passing # End time: 11:31:43 on Oct 16,2026, Elapsed time: 0:31:48 # Errors: 0, Warnings: 13