Analysis & Synthesis report for assignment2 Thu Oct 15 13:58:40 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation 5. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2025 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus Prime License Agreement, the Altera IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the Altera Software License Subscription Agreements on the Quartus Prime software download page. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ ; Analysis & Synthesis Status ; Failed - Thu Oct 15 13:58:40 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; assignment2 ; ; Top-level Entity Name ; assignment2 ; ; Family ; Cyclone V ; ; Logic utilization (in ALMs) ; N/A until Partition Merge ; ; Total registers ; N/A until Partition Merge ; ; Total pins ; N/A until Partition Merge ; ; Total virtual pins ; N/A until Partition Merge ; ; Total block memory bits ; N/A until Partition Merge ; ; Total PLLs ; N/A until Partition Merge ; ; Total DLLs ; N/A until Partition Merge ; +-----------------------------+-------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +---------------------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +---------------------------------------------------------------------------------+--------------------+--------------------+ ; Device ; 5CGXFC5C6F27C7 ; ; ; Top-level entity name ; assignment2 ; assignment2 ; ; Family name ; Cyclone V ; Cyclone V ; ; Maximum processors allowed for parallel compilation ; 2 ; ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Infer RAMs from Raw Logic ; On ; On ; ; Parallel Synthesis ; On ; On ; ; DSP Block Balancing ; Auto ; Auto ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto DSP Block Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Strict RAM Replacement ; Off ; Off ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Timing-Driven Synthesis ; On ; On ; ; Report Parameter Settings ; On ; On ; ; Report Source Assignments ; On ; On ; ; Report Connectivity Checks ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 3 ; 3 ; ; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Auto Gated Clock Conversion ; Off ; Off ; ; Block Design Naming ; Auto ; Auto ; ; SDC constraint protection ; Off ; Off ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Pre-Mapping Resynthesis Optimization ; Off ; Off ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Resource Aware Inference For Block RAM ; On ; On ; ; Automatic Parallel Synthesis ; On ; On ; ; Partial Reconfiguration Bitstream ID ; Off ; Off ; +---------------------------------------------------------------------------------+--------------------+--------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 4 ; ; Maximum allowed ; 2 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 1 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; +----------------------------+-------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Info: Processing started: Thu Oct 15 13:58:31 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 Info (20032): Parallel compilation is enabled and will use up to 2 processors Info (12021): Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Info (12023): Found entity 1: rom File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 4 Info (12023): Found entity 2: ram File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 4 Info (12023): Found entity 3: register_file File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 4 Info (12023): Found entity 4: instruction_counter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv Line: 4 Info (12023): Found entity 5: instruction_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv Line: 3 Info (12023): Found entity 6: instruction_module_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv Line: 4 Info (12023): Found entity 7: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 4 Info (12023): Found entity 8: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3 Info (12023): Found entity 9: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9 Info (12023): Found entity 10: shifter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv Line: 3 Info (12023): Found entity 11: sign_extender File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv Line: 4 Info (12023): Found entity 12: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv Line: 3 Info (12023): Found entity 13: seven_seg_4digit File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv Line: 5 Info (12023): Found entity 14: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 16 Info (12127): Elaborating entity "assignment2" for the top level hierarchy Warning (10036): Verilog HDL or VHDL warning at assignment2.sv(58): object "rd" assigned a value but never read File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 58 Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 61 Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 63 Warning (10850): Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range [0:1023] File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 16 Warning (10030): Net "mem.data_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 Warning (10030): Net "mem.waddr_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 Warning (10030): Net "mem.we_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 65 Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 72 Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 78 Info (12128): Elaborating entity "sign_extender" for hierarchy "sign_extender:SIGNEXT" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 81 Error (10043): Verilog HDL unsupported feature error at sign_extender.sv(10): Procedural Continuous Assignment to register is not supported File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv Line: 10 Error (12152): Can't elaborate user hierarchy "sign_extender:SIGNEXT" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 81 Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 5 warnings Error: Peak virtual memory: 403 megabytes Error: Processing ended: Thu Oct 15 13:58:40 2026 Error: Elapsed time: 00:00:09 Error: Total CPU time (on all processors): 00:00:23