// Copyright (C) 2025  Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Altera and sold by Altera or its authorized distributors.  Please
// refer to the Altera Software License Subscription Agreements 
// on the Quartus Prime software download page.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"

// DATE "09/15/2026 16:40:09"

// 
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
// 

// 
// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only
// 

`timescale 1 ps/ 1 ps

module asu (
	op,
	A,
	B,
	OUT_1,
	COUT,
	OUT_CIN,
	out_seg_1);
input 	[0:0] op;
input 	[3:0] A;
input 	[3:0] B;
output 	[3:0] OUT_1;
output 	[0:0] COUT;
output 	[0:0] OUT_CIN;
output 	[7:0] out_seg_1;

// Design Ports Information
// OUT_1[0]	=>  Location: PIN_F7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// OUT_1[1]	=>  Location: PIN_F6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// OUT_1[2]	=>  Location: PIN_G6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// OUT_1[3]	=>  Location: PIN_G7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// COUT[0]	=>  Location: PIN_J8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// OUT_CIN[0]	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
// out_seg_1[0]	=>  Location: PIN_A17,	 I/O Standard: 2.5 V,	 Current Strength: Default
// out_seg_1[1]	=>  Location: PIN_V19,	 I/O Standard: 1.2 V,	 Current Strength: Default
// out_seg_1[2]	=>  Location: PIN_V18,	 I/O Standard: 1.2 V,	 Current Strength: Default
// out_seg_1[3]	=>  Location: PIN_V17,	 I/O Standard: 1.2 V,	 Current Strength: Default
// out_seg_1[4]	=>  Location: PIN_W18,	 I/O Standard: 1.2 V,	 Current Strength: Default
// out_seg_1[5]	=>  Location: PIN_Y20,	 I/O Standard: 1.2 V,	 Current Strength: Default
// out_seg_1[6]	=>  Location: PIN_Y19,	 I/O Standard: 1.2 V,	 Current Strength: Default
// out_seg_1[7]	=>  Location: PIN_Y18,	 I/O Standard: 1.2 V,	 Current Strength: Default
// op[0]	=>  Location: PIN_AE19,	 I/O Standard: 1.2 V,	 Current Strength: Default
// B[3]	=>  Location: PIN_AC10,	 I/O Standard: 1.2 V,	 Current Strength: Default
// A[3]	=>  Location: PIN_AC8,	 I/O Standard: 1.2 V,	 Current Strength: Default
// B[0]	=>  Location: PIN_W11,	 I/O Standard: 1.2 V,	 Current Strength: Default
// A[0]	=>  Location: PIN_AC9,	 I/O Standard: 1.2 V,	 Current Strength: Default
// B[1]	=>  Location: PIN_AB10,	 I/O Standard: 1.2 V,	 Current Strength: Default
// A[1]	=>  Location: PIN_AE10,	 I/O Standard: 1.2 V,	 Current Strength: Default
// B[2]	=>  Location: PIN_V10,	 I/O Standard: 1.2 V,	 Current Strength: Default
// A[2]	=>  Location: PIN_AD13,	 I/O Standard: 1.2 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \~QUARTUS_CREATED_GND~I_combout ;
wire \op[0]~input_o ;
wire \A[0]~input_o ;
wire \B[0]~input_o ;
wire \Add0~22_cout ;
wire \Add0~1_sumout ;
wire \A[1]~input_o ;
wire \B[1]~input_o ;
wire \Add0~2 ;
wire \Add0~5_sumout ;
wire \A[2]~input_o ;
wire \B[2]~input_o ;
wire \Add0~6 ;
wire \Add0~9_sumout ;
wire \B[3]~input_o ;
wire \A[3]~input_o ;
wire \Add0~10 ;
wire \Add0~13_sumout ;
wire \Add0~14 ;
wire \Add0~17_sumout ;
wire \OUT_CIN~0_combout ;
wire \dut|Mux5~0_combout ;
wire \dut|Mux4~0_combout ;
wire \dut|Mux3~0_combout ;
wire \dut|Mux2~0_combout ;
wire \dut|Mux1~0_combout ;
wire \dut|Mux0~0_combout ;
wire \dut|WideOr0~0_combout ;


// Location: IOOBUF_X14_Y61_N53
cyclonev_io_obuf \OUT_1[0]~output (
	.i(\Add0~1_sumout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_1[0]),
	.obar());
// synopsys translate_off
defparam \OUT_1[0]~output .bus_hold = "false";
defparam \OUT_1[0]~output .open_drain_output = "false";
defparam \OUT_1[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X15_Y61_N36
cyclonev_io_obuf \OUT_1[1]~output (
	.i(\Add0~5_sumout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_1[1]),
	.obar());
// synopsys translate_off
defparam \OUT_1[1]~output .bus_hold = "false";
defparam \OUT_1[1]~output .open_drain_output = "false";
defparam \OUT_1[1]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X15_Y61_N53
cyclonev_io_obuf \OUT_1[2]~output (
	.i(\Add0~9_sumout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_1[2]),
	.obar());
// synopsys translate_off
defparam \OUT_1[2]~output .bus_hold = "false";
defparam \OUT_1[2]~output .open_drain_output = "false";
defparam \OUT_1[2]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X14_Y61_N36
cyclonev_io_obuf \OUT_1[3]~output (
	.i(\Add0~13_sumout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_1[3]),
	.obar());
// synopsys translate_off
defparam \OUT_1[3]~output .bus_hold = "false";
defparam \OUT_1[3]~output .open_drain_output = "false";
defparam \OUT_1[3]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X14_Y61_N19
cyclonev_io_obuf \COUT[0]~output (
	.i(\Add0~17_sumout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(COUT[0]),
	.obar());
// synopsys translate_off
defparam \COUT[0]~output .bus_hold = "false";
defparam \COUT[0]~output .open_drain_output = "false";
defparam \COUT[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X10_Y61_N42
cyclonev_io_obuf \OUT_CIN[0]~output (
	.i(\OUT_CIN~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(OUT_CIN[0]),
	.obar());
// synopsys translate_off
defparam \OUT_CIN[0]~output .bus_hold = "false";
defparam \OUT_CIN[0]~output .open_drain_output = "false";
defparam \OUT_CIN[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X55_Y61_N76
cyclonev_io_obuf \out_seg_1[0]~output (
	.i(gnd),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(out_seg_1[0]),
	.obar());
// synopsys translate_off
defparam \out_seg_1[0]~output .bus_hold = "false";
defparam \out_seg_1[0]~output .open_drain_output = "false";
defparam \out_seg_1[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X66_Y0_N2
cyclonev_io_obuf \out_seg_1[1]~output (
	.i(\dut|Mux5~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(out_seg_1[1]),
	.obar());
// synopsys translate_off
defparam \out_seg_1[1]~output .bus_hold = "false";
defparam \out_seg_1[1]~output .open_drain_output = "false";
defparam \out_seg_1[1]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X64_Y0_N2
cyclonev_io_obuf \out_seg_1[2]~output (
	.i(\dut|Mux4~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(out_seg_1[2]),
	.obar());
// synopsys translate_off
defparam \out_seg_1[2]~output .bus_hold = "false";
defparam \out_seg_1[2]~output .open_drain_output = "false";
defparam \out_seg_1[2]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X64_Y0_N19
cyclonev_io_obuf \out_seg_1[3]~output (
	.i(\dut|Mux3~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(out_seg_1[3]),
	.obar());
// synopsys translate_off
defparam \out_seg_1[3]~output .bus_hold = "false";
defparam \out_seg_1[3]~output .open_drain_output = "false";
defparam \out_seg_1[3]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X66_Y0_N19
cyclonev_io_obuf \out_seg_1[4]~output (
	.i(\dut|Mux2~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(out_seg_1[4]),
	.obar());
// synopsys translate_off
defparam \out_seg_1[4]~output .bus_hold = "false";
defparam \out_seg_1[4]~output .open_drain_output = "false";
defparam \out_seg_1[4]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X65_Y0_N2
cyclonev_io_obuf \out_seg_1[5]~output (
	.i(\dut|Mux1~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(out_seg_1[5]),
	.obar());
// synopsys translate_off
defparam \out_seg_1[5]~output .bus_hold = "false";
defparam \out_seg_1[5]~output .open_drain_output = "false";
defparam \out_seg_1[5]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X65_Y0_N19
cyclonev_io_obuf \out_seg_1[6]~output (
	.i(\dut|Mux0~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(out_seg_1[6]),
	.obar());
// synopsys translate_off
defparam \out_seg_1[6]~output .bus_hold = "false";
defparam \out_seg_1[6]~output .open_drain_output = "false";
defparam \out_seg_1[6]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X62_Y0_N42
cyclonev_io_obuf \out_seg_1[7]~output (
	.i(!\dut|WideOr0~0_combout ),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(16'b0000000000000000),
	.parallelterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(out_seg_1[7]),
	.obar());
// synopsys translate_off
defparam \out_seg_1[7]~output .bus_hold = "false";
defparam \out_seg_1[7]~output .open_drain_output = "false";
defparam \out_seg_1[7]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOIBUF_X50_Y0_N35
cyclonev_io_ibuf \op[0]~input (
	.i(op[0]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\op[0]~input_o ));
// synopsys translate_off
defparam \op[0]~input .bus_hold = "false";
defparam \op[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X14_Y0_N35
cyclonev_io_ibuf \A[0]~input (
	.i(A[0]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\A[0]~input_o ));
// synopsys translate_off
defparam \A[0]~input .bus_hold = "false";
defparam \A[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X10_Y0_N41
cyclonev_io_ibuf \B[0]~input (
	.i(B[0]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\B[0]~input_o ));
// synopsys translate_off
defparam \B[0]~input .bus_hold = "false";
defparam \B[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N30
cyclonev_lcell_comb \Add0~22 (
// Equation(s):
// \Add0~22_cout  = CARRY(( \op[0]~input_o  ) + ( VCC ) + ( !VCC ))

	.dataa(gnd),
	.datab(!\op[0]~input_o ),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(),
	.sumout(),
	.cout(\Add0~22_cout ),
	.shareout());
// synopsys translate_off
defparam \Add0~22 .extended_lut = "off";
defparam \Add0~22 .lut_mask = 64'h0000000000003333;
defparam \Add0~22 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N33
cyclonev_lcell_comb \Add0~1 (
// Equation(s):
// \Add0~1_sumout  = SUM(( \A[0]~input_o  ) + ( !\op[0]~input_o  $ (!\B[0]~input_o ) ) + ( \Add0~22_cout  ))
// \Add0~2  = CARRY(( \A[0]~input_o  ) + ( !\op[0]~input_o  $ (!\B[0]~input_o ) ) + ( \Add0~22_cout  ))

	.dataa(gnd),
	.datab(!\op[0]~input_o ),
	.datac(gnd),
	.datad(!\A[0]~input_o ),
	.datae(gnd),
	.dataf(!\B[0]~input_o ),
	.datag(gnd),
	.cin(\Add0~22_cout ),
	.sharein(gnd),
	.combout(),
	.sumout(\Add0~1_sumout ),
	.cout(\Add0~2 ),
	.shareout());
// synopsys translate_off
defparam \Add0~1 .extended_lut = "off";
defparam \Add0~1 .lut_mask = 64'h0000CC33000000FF;
defparam \Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: IOIBUF_X36_Y0_N52
cyclonev_io_ibuf \A[1]~input (
	.i(A[1]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\A[1]~input_o ));
// synopsys translate_off
defparam \A[1]~input .bus_hold = "false";
defparam \A[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X12_Y0_N35
cyclonev_io_ibuf \B[1]~input (
	.i(B[1]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\B[1]~input_o ));
// synopsys translate_off
defparam \B[1]~input .bus_hold = "false";
defparam \B[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N36
cyclonev_lcell_comb \Add0~5 (
// Equation(s):
// \Add0~5_sumout  = SUM(( !\op[0]~input_o  $ (!\B[1]~input_o ) ) + ( \A[1]~input_o  ) + ( \Add0~2  ))
// \Add0~6  = CARRY(( !\op[0]~input_o  $ (!\B[1]~input_o ) ) + ( \A[1]~input_o  ) + ( \Add0~2  ))

	.dataa(gnd),
	.datab(!\op[0]~input_o ),
	.datac(!\A[1]~input_o ),
	.datad(!\B[1]~input_o ),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(\Add0~2 ),
	.sharein(gnd),
	.combout(),
	.sumout(\Add0~5_sumout ),
	.cout(\Add0~6 ),
	.shareout());
// synopsys translate_off
defparam \Add0~5 .extended_lut = "off";
defparam \Add0~5 .lut_mask = 64'h0000F0F0000033CC;
defparam \Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: IOIBUF_X34_Y0_N35
cyclonev_io_ibuf \A[2]~input (
	.i(A[2]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\A[2]~input_o ));
// synopsys translate_off
defparam \A[2]~input .bus_hold = "false";
defparam \A[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X17_Y0_N75
cyclonev_io_ibuf \B[2]~input (
	.i(B[2]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\B[2]~input_o ));
// synopsys translate_off
defparam \B[2]~input .bus_hold = "false";
defparam \B[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N39
cyclonev_lcell_comb \Add0~9 (
// Equation(s):
// \Add0~9_sumout  = SUM(( \A[2]~input_o  ) + ( !\op[0]~input_o  $ (!\B[2]~input_o ) ) + ( \Add0~6  ))
// \Add0~10  = CARRY(( \A[2]~input_o  ) + ( !\op[0]~input_o  $ (!\B[2]~input_o ) ) + ( \Add0~6  ))

	.dataa(!\A[2]~input_o ),
	.datab(!\op[0]~input_o ),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!\B[2]~input_o ),
	.datag(gnd),
	.cin(\Add0~6 ),
	.sharein(gnd),
	.combout(),
	.sumout(\Add0~9_sumout ),
	.cout(\Add0~10 ),
	.shareout());
// synopsys translate_off
defparam \Add0~9 .extended_lut = "off";
defparam \Add0~9 .lut_mask = 64'h0000CC3300005555;
defparam \Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: IOIBUF_X12_Y0_N52
cyclonev_io_ibuf \B[3]~input (
	.i(B[3]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\B[3]~input_o ));
// synopsys translate_off
defparam \B[3]~input .bus_hold = "false";
defparam \B[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X14_Y0_N52
cyclonev_io_ibuf \A[3]~input (
	.i(A[3]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\A[3]~input_o ));
// synopsys translate_off
defparam \A[3]~input .bus_hold = "false";
defparam \A[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N42
cyclonev_lcell_comb \Add0~13 (
// Equation(s):
// \Add0~13_sumout  = SUM(( !\op[0]~input_o  $ (!\B[3]~input_o ) ) + ( \A[3]~input_o  ) + ( \Add0~10  ))
// \Add0~14  = CARRY(( !\op[0]~input_o  $ (!\B[3]~input_o ) ) + ( \A[3]~input_o  ) + ( \Add0~10  ))

	.dataa(gnd),
	.datab(!\op[0]~input_o ),
	.datac(!\B[3]~input_o ),
	.datad(gnd),
	.datae(gnd),
	.dataf(!\A[3]~input_o ),
	.datag(gnd),
	.cin(\Add0~10 ),
	.sharein(gnd),
	.combout(),
	.sumout(\Add0~13_sumout ),
	.cout(\Add0~14 ),
	.shareout());
// synopsys translate_off
defparam \Add0~13 .extended_lut = "off";
defparam \Add0~13 .lut_mask = 64'h0000FF0000003C3C;
defparam \Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N45
cyclonev_lcell_comb \Add0~17 (
// Equation(s):
// \Add0~17_sumout  = SUM(( GND ) + ( GND ) + ( \Add0~14  ))

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(\Add0~14 ),
	.sharein(gnd),
	.combout(),
	.sumout(\Add0~17_sumout ),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \Add0~17 .extended_lut = "off";
defparam \Add0~17 .lut_mask = 64'h0000FFFF00000000;
defparam \Add0~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N0
cyclonev_lcell_comb \OUT_CIN~0 (
// Equation(s):
// \OUT_CIN~0_combout  = ( \op[0]~input_o  & ( !\A[3]~input_o  $ (!\B[3]~input_o  $ (!\Add0~13_sumout )) ) ) # ( !\op[0]~input_o  & ( !\A[3]~input_o  $ (!\B[3]~input_o  $ (\Add0~13_sumout )) ) )

	.dataa(gnd),
	.datab(!\A[3]~input_o ),
	.datac(!\B[3]~input_o ),
	.datad(!\Add0~13_sumout ),
	.datae(!\op[0]~input_o ),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\OUT_CIN~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \OUT_CIN~0 .extended_lut = "off";
defparam \OUT_CIN~0 .lut_mask = 64'h3CC3C33C3CC3C33C;
defparam \OUT_CIN~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N9
cyclonev_lcell_comb \dut|Mux5~0 (
// Equation(s):
// \dut|Mux5~0_combout  = ( !\Add0~5_sumout  & ( \Add0~9_sumout  & ( !\Add0~1_sumout  $ (\Add0~13_sumout ) ) ) ) # ( \Add0~5_sumout  & ( !\Add0~9_sumout  & ( (\Add0~1_sumout  & \Add0~13_sumout ) ) ) ) # ( !\Add0~5_sumout  & ( !\Add0~9_sumout  & ( 
// (\Add0~1_sumout  & !\Add0~13_sumout ) ) ) )

	.dataa(!\Add0~1_sumout ),
	.datab(gnd),
	.datac(!\Add0~13_sumout ),
	.datad(gnd),
	.datae(!\Add0~5_sumout ),
	.dataf(!\Add0~9_sumout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dut|Mux5~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dut|Mux5~0 .extended_lut = "off";
defparam \dut|Mux5~0 .lut_mask = 64'h50500505A5A50000;
defparam \dut|Mux5~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N12
cyclonev_lcell_comb \dut|Mux4~0 (
// Equation(s):
// \dut|Mux4~0_combout  = ( \Add0~5_sumout  & ( \Add0~9_sumout  & ( (!\Add0~1_sumout ) # (\Add0~13_sumout ) ) ) ) # ( !\Add0~5_sumout  & ( \Add0~9_sumout  & ( !\Add0~13_sumout  $ (!\Add0~1_sumout ) ) ) ) # ( \Add0~5_sumout  & ( !\Add0~9_sumout  & ( 
// (\Add0~13_sumout  & \Add0~1_sumout ) ) ) )

	.dataa(gnd),
	.datab(!\Add0~13_sumout ),
	.datac(!\Add0~1_sumout ),
	.datad(gnd),
	.datae(!\Add0~5_sumout ),
	.dataf(!\Add0~9_sumout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dut|Mux4~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dut|Mux4~0 .extended_lut = "off";
defparam \dut|Mux4~0 .lut_mask = 64'h000003033C3CF3F3;
defparam \dut|Mux4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N51
cyclonev_lcell_comb \dut|Mux3~0 (
// Equation(s):
// \dut|Mux3~0_combout  = ( \Add0~5_sumout  & ( \Add0~9_sumout  & ( \Add0~13_sumout  ) ) ) # ( !\Add0~5_sumout  & ( \Add0~9_sumout  & ( (!\Add0~1_sumout  & \Add0~13_sumout ) ) ) ) # ( \Add0~5_sumout  & ( !\Add0~9_sumout  & ( (!\Add0~1_sumout  & 
// !\Add0~13_sumout ) ) ) )

	.dataa(!\Add0~1_sumout ),
	.datab(gnd),
	.datac(!\Add0~13_sumout ),
	.datad(gnd),
	.datae(!\Add0~5_sumout ),
	.dataf(!\Add0~9_sumout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dut|Mux3~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dut|Mux3~0 .extended_lut = "off";
defparam \dut|Mux3~0 .lut_mask = 64'h0000A0A00A0A0F0F;
defparam \dut|Mux3~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N24
cyclonev_lcell_comb \dut|Mux2~0 (
// Equation(s):
// \dut|Mux2~0_combout  = ( \Add0~5_sumout  & ( \Add0~9_sumout  & ( \Add0~1_sumout  ) ) ) # ( !\Add0~5_sumout  & ( \Add0~9_sumout  & ( (!\Add0~13_sumout  & !\Add0~1_sumout ) ) ) ) # ( \Add0~5_sumout  & ( !\Add0~9_sumout  & ( (\Add0~13_sumout  & 
// !\Add0~1_sumout ) ) ) ) # ( !\Add0~5_sumout  & ( !\Add0~9_sumout  & ( \Add0~1_sumout  ) ) )

	.dataa(gnd),
	.datab(!\Add0~13_sumout ),
	.datac(!\Add0~1_sumout ),
	.datad(gnd),
	.datae(!\Add0~5_sumout ),
	.dataf(!\Add0~9_sumout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dut|Mux2~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dut|Mux2~0 .extended_lut = "off";
defparam \dut|Mux2~0 .lut_mask = 64'h0F0F3030C0C00F0F;
defparam \dut|Mux2~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N21
cyclonev_lcell_comb \dut|Mux1~0 (
// Equation(s):
// \dut|Mux1~0_combout  = ( \Add0~5_sumout  & ( \Add0~9_sumout  & ( (\Add0~1_sumout  & !\Add0~13_sumout ) ) ) ) # ( !\Add0~5_sumout  & ( \Add0~9_sumout  & ( !\Add0~13_sumout  ) ) ) # ( \Add0~5_sumout  & ( !\Add0~9_sumout  & ( (\Add0~1_sumout  & 
// !\Add0~13_sumout ) ) ) ) # ( !\Add0~5_sumout  & ( !\Add0~9_sumout  & ( \Add0~1_sumout  ) ) )

	.dataa(!\Add0~1_sumout ),
	.datab(gnd),
	.datac(!\Add0~13_sumout ),
	.datad(gnd),
	.datae(!\Add0~5_sumout ),
	.dataf(!\Add0~9_sumout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dut|Mux1~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dut|Mux1~0 .extended_lut = "off";
defparam \dut|Mux1~0 .lut_mask = 64'h55555050F0F05050;
defparam \dut|Mux1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N54
cyclonev_lcell_comb \dut|Mux0~0 (
// Equation(s):
// \dut|Mux0~0_combout  = ( \Add0~9_sumout  & ( (\Add0~1_sumout  & (!\Add0~13_sumout  $ (!\Add0~5_sumout ))) ) ) # ( !\Add0~9_sumout  & ( (!\Add0~13_sumout  & ((\Add0~5_sumout ) # (\Add0~1_sumout ))) ) )

	.dataa(!\Add0~1_sumout ),
	.datab(!\Add0~13_sumout ),
	.datac(!\Add0~5_sumout ),
	.datad(gnd),
	.datae(gnd),
	.dataf(!\Add0~9_sumout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dut|Mux0~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dut|Mux0~0 .extended_lut = "off";
defparam \dut|Mux0~0 .lut_mask = 64'h4C4C4C4C14141414;
defparam \dut|Mux0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y1_N57
cyclonev_lcell_comb \dut|WideOr0~0 (
// Equation(s):
// \dut|WideOr0~0_combout  = ( \Add0~9_sumout  & ( (!\Add0~1_sumout  & ((!\Add0~13_sumout ) # (\Add0~5_sumout ))) # (\Add0~1_sumout  & ((!\Add0~5_sumout ) # (\Add0~13_sumout ))) ) ) # ( !\Add0~9_sumout  & ( (\Add0~5_sumout ) # (\Add0~13_sumout ) ) )

	.dataa(!\Add0~1_sumout ),
	.datab(!\Add0~13_sumout ),
	.datac(gnd),
	.datad(!\Add0~5_sumout ),
	.datae(gnd),
	.dataf(!\Add0~9_sumout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\dut|WideOr0~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \dut|WideOr0~0 .extended_lut = "off";
defparam \dut|WideOr0~0 .lut_mask = 64'h33FF33FFDDBBDDBB;
defparam \dut|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y49_N0
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\~QUARTUS_CREATED_GND~I_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
// synopsys translate_on

endmodule