m255 K4 z2 !s11f vlog 2020.1 2020.02, Feb 28 2020 13 !s112 1.1 !i10d 8192 !i10e 25 !i10f 100 cModel Technology d/home/oliver/intelFPGA/20.1/modelsim_ase/bin valu Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3 Z1 !s110 1789448641 !i10b 1 !s100 Kh9ZlG?nRa:nnklUM3MaM0 Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1 IlI`[:Ol82B@F8AM_FVkV41 Z3 VDg1SIo80bB@j0V0VzS_@n1 S1 Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim Z5 w1789355084 8alu.sv Falu.sv !i122 18 L0 9 28 Z6 OV;L;2020.1;71 r1 !s85 0 31 Z7 !s108 1789448641.000000 Z8 !s107 lu.sv|asu.sv|alu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv| Z9 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv| !i113 1 Z10 o-work work -sv Z11 tCvgOpt 0 valu_tb R0 R1 !i10b 1 !s100 8=>8o`KV]hRM]V8AV?S[C1 R2 Iz[VXe9HJ@koSDFNR185;i1 R3 S1 R4 R5 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv !i122 18 L0 3 214 R6 r1 !s85 0 31 R7 R8 R9 !i113 1 R10 R11 vasu R0 R1 !i10b 1 !s100 MiS^hmH6XEfHgJYg=7c;32 R2 I<S]N8CcV@e24ZMO?A3 R2 INFK7`kK]UQzEBD`:U7gC70 R3 S1 R4 Z12 w1788926090 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv !i122 16 L0 3 120 R6 r1 !s85 0 31 !s108 1789448473.000000 !s107 asu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv| !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv| !i113 1 R10 R11 vinstruction_classifier R0 Z13 !s110 1789448904 !i10b 1 !s100 LBO=Ba0m3b@J?;=_fd^7P3 R2 I[MC9A^:kRAc`nk8eJ6i8o;@kY_?aVJn:d3 R3 S1 R4 R5 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv !i122 22 L0 2 51 R6 r1 !s85 0 31 R14 R15 R16 !i113 1 R10 R11 vlu R0 Z17 !s110 1789449208 !i10b 1 !s100 H5AG9eSQKJkS4F`0;5hWl0 R2 IObN^<8?MCaP;K@UKCVaP^1 R3 S1 R4 R5 8lu.sv Flu.sv !i122 26 Z18 L0 3 16 R6 r1 !s85 0 31 Z19 !s108 1789449208.000000 !s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv| Z20 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv| !i113 1 R10 R11 vlu_tb R0 R17 !i10b 1 !s100 AE_liX6DCD[3>b;K6Wgf72 R2 IC?h=m;SY77_D:GA0FRi`]oD>7BNB:Rd?3 R2 IedFU7?nB5ZOibY?bC8=L41 R3 S1 R4 R5 8seven_seg.sv Fseven_seg.sv !i122 24 L0 3 23 R6 r1 !s85 0 31 Z23 !s108 1789449021.000000 Z24 !s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv| Z25 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv| !i113 1 R10 R11 vseven_seg_tb R0 R22 !i10b 1 !s100 jPijM2]zTRBV8TFdD?Q`I1 R2 I_mSF@Md^k^GhHm5;W4U_=0 R3 S1 R4 w1788418794 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv !i122 24 L0 3 66 R6 r1 !s85 0 31 R23 R24 R25 !i113 1 R10 R11 vshifter R0 Z26 !s110 1789448794 !i10b 1 !s100