`ifndef ASS_2_SV
`define ASS_2_SV

`ifdef SYNTHESIS
	`include "../../rom.sv"
    `include "../../ram.sv"
    `include "../../register_file.sv"
    `include "../../instruction_counter.sv"
    `include "../../instruction_classifier.sv"
    `include "../../instruction_module_classifier.sv"
    `include "../../alu.sv"
    `include "../../shifter.sv"
`else
	`include "rom.sv"
    `include "ram.sv"
    `include "register_file.sv"
    `include "instruction_counter.sv"
    `include "instruction_classifier.sv"
    `include "instruction_module_classifier.sv"
    `include "alu.sv"
    `include "shifter.sv"
`endif



module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
    logic [romsz-1:0] pc_addr;
    logic [romsz-1:0] pc_addr_write;
    logic [0:0] pc_we;
    logic [2**width-1:0] instruction;

    logic[0:0] R;
    logic[0:0] B1;
    logic[0:0] J;
    logic[0:0] B2;
    logic[0:0] I;
    logic[0:0] F;
    logic[0:0] M;

    logic [0:0] en_shifter;
    logic [0:0] en_jmp;
    logic [0:0] en_mul;
    logic [0:0] en_alu;

    logic [1:0] flags;
    logic [2**width-1:0] rs;
    logic [2**width-1:0] rt;
    logic [2**width-1:0] rd;
    logic [0:0] rd_we;

    instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
    rom #(romsz, 2**width) ROM (pc_addr, instruction);
    instruction_classifier INSTRUCTION_CLASSIFIER(instruction[31:26], R, B1, J, B2, I, F, M);
    instruction_module_classifier INSTRUCTION_MODULE_CLASSIFIER(instruction[5:3], en_shifter, en_jmp, en_mul, en_alu);
    
    register_file #(width, 5) REGS (clk,
        rd_we, instruction[15:11],
        rs, instruction[25:21],
        rt, instruction[20:16]
    );

    logic [2**width-1:0] rd_alu;
    alu #(width) ALU (instruction[3:0], rs, rt, rd_alu, flags[1:0]);

    logic [2**width-1:0] rd_shifter;
    shifter #(width) SHIFTER (instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
    
   assign rd = en_alu
          ? rd_alu
          : (en_shifter ? rd_shifter : {2**width{1'b0}});

endmodule
`endif