// Copyright (C) 2025  Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Altera and sold by Altera or its authorized distributors.  Please
// refer to the Altera Software License Subscription Agreements 
// on the Quartus Prime software download page.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"

// DATE "10/13/2026 13:24:10"

// 
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
// 

// 
// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only
// 

`timescale 1 ps/ 1 ps

module assignment2 (
	clk);
input 	logic [0:0] clk ;

// Design Ports Information
// clk[0]	=>  Location: PIN_M21,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \clk[0]~input_o ;
wire \~QUARTUS_CREATED_GND~I_combout ;


// Location: IOIBUF_X68_Y32_N61
cyclonev_io_ibuf \clk[0]~input (
	.i(clk[0]),
	.ibar(gnd),
	.dynamicterminationcontrol(gnd),
	.o(\clk[0]~input_o ));
// synopsys translate_off
defparam \clk[0]~input .bus_hold = "false";
defparam \clk[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LABCELL_X9_Y53_N0
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\~QUARTUS_CREATED_GND~I_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
// synopsys translate_on

endmodule