{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1792035814963 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792035814963 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 15 14:43:34 2026 " "Processing started: Thu Oct 15 14:43:34 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792035814963 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035814963 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035814964 ""}
{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1792035815265 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 14 14 " "Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" {  } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" {  } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" {  } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" {  } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" {  } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" {  } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" {  } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" {  } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" {  } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" {  } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "11 sign_extender " "Found entity 11: sign_extender" {  } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg " "Found entity 12: seven_seg" {  } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "13 seven_seg_4digit " "Found entity 13: seven_seg_4digit" {  } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""} { "Info" "ISGN_ENTITY_NAME" "14 assignment2 " "Found entity 14: assignment2" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792035824809 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035824809 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1792035824965 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(58) " "Verilog HDL or VHDL warning at assignment2.sv(58): object \"rd\" assigned a value but never read" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 58 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1792035824966 "|assignment2"}
{ "Error" "EVRFX_SV_TYPES_CANT_BE_ASSIGNED" "packed array unpacked array types do not match assignment2.sv(80) " "SystemVerilog error at assignment2.sv(80): packed array type cannot be assigned to unpacked array type - types do not match" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 80 0 0 } }  } 0 10928 "SystemVerilog error at %4!s!: %1!s! type cannot be assigned to %2!s! type - %3!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035824969 ""}
{ "Error" "EVRFX_SV_1071_UNCONVERTED" "RD2 assignment2.sv(80) " "SystemVerilog error at assignment2.sv(80): can't pass value from formal output RD2 to actual with incompatible type" {  } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 80 0 0 } }  } 0 10715 "SystemVerilog error at %2!s!: can't pass value from formal output %1!s! to actual with incompatible type" 0 0 "Analysis & Synthesis" 0 -1 1792035824969 ""}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Can't elaborate top-level user hierarchy" {  } {  } 0 12153 "Can't elaborate top-level user hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1792035824970 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "397 " "Peak virtual memory: 397 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792035825024 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Oct 15 14:43:45 2026 " "Processing ended: Thu Oct 15 14:43:45 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792035825024 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1792035825024 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1792035825024 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035825024 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 1  " "Quartus Prime Full Compilation was unsuccessful. 5 errors, 1 warning" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792035825689 ""}