`ifndef ALU_H_SV
`define ALU_H_SV

`include "asu.sv"
`include "lu.sv"
`include "seven_seg.sv"

// flags[0:0] = Cout
// flags[1:1] = Overflow
module alu #(parameter width=2)(input logic [3:0] op,
    input logic [2**width-1:0] A, input logic [2**width-1:0] B,
    output logic [2**width-1:0] OUT_1, output logic[1:0] flags
`ifdef SYNTHESIS
	, output logic [7:0] out_seg1);
`else
    );
`endif

    logic [0:0] asu_op;
    logic [2**width-1:0] asu_out;
    logic [1:0] asu_flags;
    logic [7:0] asu_seven_seg_out;

    // NOTE: For demo only
    // TODO: Strip this for assignment 2
    `ifdef SYNTHESIS
        asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1], asu_seven_seg_out);
    `else
        asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
    `endif

    logic [2**width-1:0] lu_out;
    lu #(width) logic_unit(op[1:0], A, B, lu_out);

    always_comb begin
        case (op) 
            4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
            4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
            4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
            4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
            4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end
            4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end
            4'b0110: begin OUT_1 = lu_out;  flags = asu_flags; end
            4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end
            4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
            4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
            default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
        endcase
    end

    // NOTE: For demo only
    // TODO: Strip this for assignment 2
    `ifdef SYNTHESIS
	    seven_seg dut(OUT_1, 1'b1, out_seg1);
    `endif
endmodule
`endif