# Loading project Assignment_1_Q3 # Compile of asu.sv was successful. # Compile of asu_tb.sv was successful. # 2 compiles, 0 failed with no errors. vsim work.asu_tb # vsim work.asu_tb # Start time: 15:01:26 on Sep 15,2026 # Loading sv_std.std # Loading work.asu_tb # Loading work.asu add wave -position end sim:/asu_tb/op add wave -position end sim:/asu_tb/A add wave -position end sim:/asu_tb/B add wave -position end sim:/asu_tb/C add wave -position end sim:/asu_tb/Cout add wave -position end sim:/asu_tb/Cin run # Beginning ASU tests # All ASU tests passing quit -sim # End time: 15:03:03 on Sep 15,2026, Elapsed time: 0:01:37 # Errors: 0, Warnings: 2 # reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini # Loading project Assignment_1_Q4 # Compile of alu.sv was successful. # Compile of alu_tb.sv was successful. # 2 compiles, 0 failed with no errors. vsim work.alu_tb # vsim work.alu_tb # Start time: 15:04:11 on Sep 15,2026 # Loading sv_std.std # Loading work.alu_tb # Loading work.alu # Loading work.asu # Loading work.lu add wave -position end sim:/alu_tb/op_in add wave -position end sim:/alu_tb/A_in add wave -position end sim:/alu_tb/B_in add wave -position end sim:/alu_tb/Y_out add wave -position end sim:/alu_tb/flags_out add wave -position end sim:/alu_tb/ops run # Beginning ALU tests # All ALU tests passing add wave -position end sim:/alu_tb/error_count run quit -sim # End time: 15:05:53 on Sep 15,2026, Elapsed time: 0:01:42 # Errors: 0, Warnings: 5 # reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini # Loading project Assignment_1_Q5 # Compile of shifter.sv was successful. # Compile of shifter_tb.sv was successful. # 2 compiles, 0 failed with no errors. vsim work.shifter_tb # vsim work.shifter_tb # Start time: 15:06:46 on Sep 15,2026 # Loading sv_std.std # Loading work.shifter_tb # Loading work.shifter add wave -position end sim:/shifter_tb/op add wave -position end sim:/shifter_tb/Y add wave -position end sim:/shifter_tb/A_in add wave -position end sim:/shifter_tb/B_in add wave -position end sim:/shifter_tb/C_in add wave -position end sim:/shifter_tb/A add wave -position end sim:/shifter_tb/B add wave -position end sim:/shifter_tb/C add wave -position end sim:/shifter_tb/Y add wave -position end sim:/shifter_tb/op run # Beginning Shifter tests # All Shifter tests passing quit -sim # End time: 15:07:54 on Sep 15,2026, Elapsed time: 0:01:08 # Errors: 0, Warnings: 5 # reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini # Loading project Assignment_1_Q6 # Compile of instruction_classifier.sv was successful. # Compile of instruction_classifier_tb.sv was successful. # 2 compiles, 0 failed with no errors. vsim work.instruction_classifier_tb # vsim work.instruction_classifier_tb # Start time: 15:08:34 on Sep 15,2026 # Loading sv_std.std # Loading work.instruction_classifier_tb # Loading work.instruction_classifier add wave -position end sim:/instruction_classifier_tb/op add wave -position end sim:/instruction_classifier_tb/C add wave -position end sim:/instruction_classifier_tb/ops run # Beginning Instruction Classifier tests # All Instruction Classifier tests passing quit -sim # End time: 15:09:45 on Sep 15,2026, Elapsed time: 0:01:11 # Errors: 0, Warnings: 5 # reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini # Loading project Assignment_1_Q1 # Compile of seven_seg.sv was successful. # Compile of seven_seg_tb.sv was successful. # 2 compiles, 0 failed with no errors. vsim work.seven_seg_tb # vsim work.seven_seg_tb # Start time: 15:10:28 on Sep 15,2026 # Loading sv_std.std # Loading work.seven_seg_tb # Loading work.seven_seg add wave -position end sim:/seven_seg_tb/in_rbi_inv add wave -position end sim:/seven_seg_tb/out_segments add wave -position end sim:/seven_seg_tb/true_segments add wave -position end sim:/seven_seg_tb/N add wave -position end sim:/seven_seg_tb/i add wave -position 1 sim:/seven_seg_tb/in_num run # Beginning seven-segment tests # All seven-segment tests passing quit -sim # End time: 15:12:28 on Sep 15,2026, Elapsed time: 0:02:00 # Errors: 0, Warnings: 5 project open /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/Assignment_1_Q2 # reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini # Loading project Assignment_1_Q2 # Compile of lu.sv was successful. # Compile of lu_tb.sv was successful. # 2 compiles, 0 failed with no errors. vsim work.lu_tb # vsim work.lu_tb # Start time: 15:13:40 on Sep 15,2026 # Loading sv_std.std # Loading work.lu_tb # Loading work.lu add wave -position end sim:/lu_tb/op add wave -position end sim:/lu_tb/A add wave -position end sim:/lu_tb/B add wave -position end sim:/lu_tb/C run # Beginning LU tests # All LU tests passing quit -sim # End time: 15:14:33 on Sep 15,2026, Elapsed time: 0:00:53 # Errors: 0, Warnings: 3