`ifndef SHIFTER_H_SV
`define SHIFTER_H_SV
module shifter #(width=2)(input logic [2:0] op,
    input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C, 
    output logic[2**width-1:0] OUT_1);
// A and B are 2^n bits wide and C is n bits wide as according to the docs
    always_comb begin
        case (op)
            3'b000: OUT_1 = A << C;
            3'b001: OUT_1 = A >> C;
            3'b011: OUT_1 = $signed(A) >>> C;
            3'b100: OUT_1 = A << B;
            3'b101: OUT_1 = A >> B;
            3'b111: OUT_1 = $signed(A) >>> B;
            default:OUT_1 = A;
        endcase
    end    
endmodule
`endif