Added some delay to better test final branch/halt.

modules/ram.sv

@@ -5,8 +5,8 @@ module ram #(addrwidth=9, datawidth=5)(
     input logic [0:0] clk, input logic [0:0] rst,
     input logic [addrwidth-1:0] addr,
     input logic [0:0] we,
-    input logic [datawidth-1:0] data_in,
+    input logic [2**datawidth-1:0] data_in,
-    output logic [datawidth-1:0] data_out
+    output logic [2**datawidth-1:0] data_out
 );
 
     // TODO: Make this byte-sized, NOT word-sized!

modules/sign_extender.sv

@@ -7,7 +7,7 @@ module sign_extender #(in_width=4, out_width=5)(
     output logic [2**out_width-1:0] ext_val
 );
     logic [0:0] msb;
-    assign msb = (val & {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1);
+    assign msb = (val && {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1);
     always_comb begin
         if (op) begin
             ext_val = { {(2**(out_width-in_width)){msb}}, val};

tests/mips.sv

@@ -39,6 +39,7 @@ module mips_tb();
 		$dumpvars(5, CPU.instruction);
 		$dumpvars(5, CPU.ALU);
 		$dumpvars(6, CPU.flags);
+        $dumpvars(7, CPU.rt_imm);
 
         // Zero out lower registers
         $display("Beginning MIPS tests");
@@ -96,6 +97,10 @@ module mips_tb();
 
         // Final state check
         #2;
+        #2;
+        #2;
+        #2;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[8]  == 32'd10);
         `TEST_CHECK(CPU.REGS.regs[9]  == 32'd7);
         `TEST_CHECK(CPU.REGS.regs[10] == 32'd7);