Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

modules/assignment2.sv

@@ -3,30 +3,67 @@
 
 `ifdef SYNTHESIS
 	`include "../../rom.sv"
-	`include "../../ram.sv"
-	`include "../../instruction_counter.sv"
-	`include "../../instruction_classifier.sv"
-	`include "../../alu.sv"
+    `include "../../ram.sv"
+    `include "../../register_file.sv"
+    `include "../../instruction_counter.sv"
+    `include "../../instruction_classifier.sv"
+    `include "../../instruction_module_classifier.sv"
+    `include "../../alu.sv"
+    `include "../../shifter.sv"
 `else
 	`include "rom.sv"
-	`include "ram.sv"
-	`include "instruction_counter.sv"
-	`include "instruction_classifier.sv"
-	`include "alu.sv"
+    `include "ram.sv"
+    `include "register_file.sv"
+    `include "instruction_counter.sv"
+    `include "instruction_classifier.sv"
+    `include "instruction_module_classifier.sv"
+    `include "alu.sv"
+    `include "shifter.sv"
 `endif
 
 
 
 module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
-    
     logic [romsz-1:0] pc_addr;
+    logic [romsz-1:0] pc_addr_write;
     logic [0:0] pc_we;
     logic [2**width-1:0] instruction;
 
-    instruction_counter pc #(romsz)(clk, pc_we, pc_addr, pc_addr);
-    ROM rom #(romsz, 2**width)();
-    RAM ram #(ramsz,  2**width)();
-    alu alu #(width)();
+    logic[0:0] R;
+    logic[0:0] B1;
+    logic[0:0] J;
+    logic[0:0] B2;
+    logic[0:0] I;
+    logic[0:0] F;
+    logic[0:0] M;
+
+    logic [0:0] en_shifter;
+    logic [0:0] en_jmp;
+    logic [0:0] en_mul;
+    logic [0:0] en_alu;
+
+    logic [1:0] flags;
+    logic [2**width-1:0] rs;
+    logic [2**width-1:0] rt;
+    logic [2**width-1:0] rd;
+    logic [0:0] rd_we;
+
+    instruction_counter PC #(romsz)(clk, pc_we, pc_addr, pc_addr_write);
+    rom ROM #(romsz, 2**width)(pc_addr, instruction);
+    instruction_classifier INSTRUCTION_CLASSIFIER(instruction[31:26], R, B1, J, B2, I, F, M);
+    instruction_module_classifier INSTRUCTION_MODULE_CLASSIFIER(instruction[5:3], en_shifter, en_jmp, en_mul, en_alu);
+    
+    register_file REGS #(width, 32)(clk,
+        rd_we, instruction[15:11],
+        rs, instruction[25:21],
+        rt, instruction[20:16]
+    );
+
+    logic [2**width-1:0] rd_alu;
+    alu ALU #(width)(instruction[3:0], rs, rt, rd_alu, flags[1:0]);
+
+    logic [2**width-1:0] rd_shifter;
+    shifter SHIFTER #(width)(instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
     
 endmodule
 

modules/instruction_module_classifier.sv

@@ -0,0 +1,18 @@
+`ifndef INSTRUCTION_CLASSIFIER_H_SV
+`define INSTRUCTION_CLASSIFIER_H_SV
+
+module instruction_module_classifier(
+    input logic [2:0] op,
+    output logic en_shifter,
+    output logic en_jmp,
+    output logic en_mul,
+    output logic en_alu,
+);
+    always_comb begin
+        en_shifter = (op & 3'b111) == 3'b000;
+        en_jmp = (op & 3'b111) == 3'b001;
+        en_mul = (op & 3'b110) == 3'b010;
+        en_alu = (op & 3'b100) == 3'b100;
+    end
+endmodule
+`endif