Fixed parameter ordering in instancing

modules/assignment2.sv

@@ -48,22 +48,22 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
     logic [2**width-1:0] rd;
     logic [0:0] rd_we;
 
-    instruction_counter PC #(width)(clk, pc_we, pc_addr_write, pc_addr);
-    rom ROM #(romsz, 2**width)(pc_addr, instruction);
+    instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
+    rom #(romsz, 2**width) ROM (pc_addr, instruction);
     instruction_classifier INSTRUCTION_CLASSIFIER(instruction[31:26], R, B1, J, B2, I, F, M);
     instruction_module_classifier INSTRUCTION_MODULE_CLASSIFIER(instruction[5:3], en_shifter, en_jmp, en_mul, en_alu);
     
-    register_file REGS #(width, 32)(clk,
+    register_file #(width, 5) REGS (clk,
         rd_we, instruction[15:11],
         rs, instruction[25:21],
         rt, instruction[20:16]
     );
 
     logic [2**width-1:0] rd_alu;
-    alu ALU #(width)(instruction[3:0], rs, rt, rd_alu, flags[1:0]);
+    alu #(width) ALU (instruction[3:0], rs, rt, rd_alu, flags[1:0]);
 
     logic [2**width-1:0] rd_shifter;
-    shifter SHIFTER #(width)(instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
+    shifter #(width) SHIFTER (instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
     
     rd = en_alu ? rd_alu : (en_shifter ? : rd_shifter : ({(2**width){1'b0}}));
 endmodule

modules/register_file.sv

@@ -1,14 +1,14 @@
 `ifndef REGISTER_FILE_H
 `define REGISTER_FILE_H
 
-module register_file #(parameter width=5, parameter nregs=32)(
+module register_file #(parameter width=5, parameter nregs=5)(
     input logic [0:0] clk, input logic[0:0] we,
-    input logic [$clog(nregs)-1:0] WA, input logic [2**width-1:0] WD,
-    input logic [$clog(nregs)-1:0] RA1, output logic [2**width-1:0] RD1,
-    input logic [$clog(nregs)-1:0] RA2, output logic [2**width-1:0] RD2
+    input logic [nregs-1:0] WA, input logic [2**width-1:0] WD,
+    input logic [nregs-1:0] RA1, output logic [2**width-1:0] RD1,
+    input logic [nregs-1:0] RA2, output logic [2**width-1:0] RD2
 );
     localparam BW = 2**width;
-    logic [2**width-1:0] regs[nregs];
+    logic [2**width-1:0] regs[2**nregs];
 
     initial begin
         regs[0] = {(2**width){1'b0}};