TroubleElectrical/FPGA_Uni
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base: TroubleElectrical/FPGA_Uni:a73990b2424fb3c5841291f1579b1fa386030ec1
TroubleElectrical/FPGA_Uni:main TroubleElectrical/FPGA_Uni:assignment-1-submission
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compare: TroubleElectrical/FPGA_Uni:e9feb3cb8d99eb8dbc69302bf19d0b73de0c1f36
TroubleElectrical/FPGA_Uni:main TroubleElectrical/FPGA_Uni:assignment-1-submission
2 Commits
a73990b242 .. e9feb3cb8d
Author SHA1 Message Date
riley e9feb3cb8d Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-09-10 15:38:50 +10:00
riley 669357ccc0 Implemented ALU. Still needs testbench and testing done. 2026-09-10 15:38:36 +10:00
1 changed files with 16 additions and 4 deletions
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modules/alu.sv
+16 -4
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@@ -9,12 +9,24 @@ module alu #(parameter width=2)(input logic [3:0] op,
logic [2**width-1:0] asu_out; logic [2**width-1:0] asu_out;
logic [1:0] asu_flags; logic [1:0] asu_flags;
logic [0:0] asu_op; asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_flags[1]);
logic [width-1:0] lu_out; logic [width-1:0] lu_out;
lu #(width) logic_unit(op[1:0], A, B, lu_out); lu #(width) logic_unit(op[1:0], A, B, lu_out);
// Cout = asu_flags[0] always_comb begin
// Overflow = asu_flags[0] ^ asu_flags[1] case (op)
2'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
2'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
2'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
2'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
2'b0100: OUT_1 = lu_out;
2'b0101: OUT_1 = lu_out;
2'b0110: OUT_1 = lu_out;
2'b0111: OUT_1 = lu_out;
2'b1010: OUT_1 = (asu_out[$clog2(width)-1] ^ asu_flags[1]);
2'b1011: OUT_1 = ~asu_flags[0];
default: '0;
endcase
end
endmodule endmodule