Added explicit rst input to RAM and PC as well as the MIPS processor.

modules/alu.sv

@@ -6,6 +6,7 @@
 
 // flags[0:0] = Cout
 // flags[1:1] = Overflow
+// flags[2:2] = Zero
 module alu #(parameter width=2)(input logic [3:0] op,
     input logic [2**width-1:0] A, input logic [2**width-1:0] B,
     output logic [2**width-1:0] OUT_1, output logic[2:0] flags

modules/assignment2.sv

@@ -13,7 +13,7 @@
 
 
 module assignment2 #(width=5, ramsz=9, romsz=10) (
-	input logic [0:0] clk
+	input logic [0:0] clk, input logic [0:0] rst
 `ifdef QUARTUS_SYNTH
     ,
 	input logic [4:0] HID_Register,
@@ -56,12 +56,12 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [2**width-1:0] rd_alu;
 	logic [2**width-1:0] rt_alu;
 	
-	instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
+	instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
 	
 	rom #(romsz, width) ROM (pc_addr, instruction);
 
 	logic [2**width-1:0] rd_mem;
-	ram #(ramsz, width) RAM (clk, rd_alu, M2W, rt, rd_mem);
+	ram #(ramsz, width) RAM (clk, rst, rd_alu, M2W, rt, rd_mem);
 	
 	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
 		M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW

modules/instruction_counter.sv

@@ -2,19 +2,17 @@
 `define INSTRUCTION_COUNTER_H
 
 module instruction_counter #(parameter width=5)(
-    input logic [0:0] clk, input logic [0:0] we,
+    input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] we,
     input logic [2**width-1:0] W,
     output logic [2**width-1:0] addr
 );
 
     logic [2**width-1:0] pc;
-
+    
-    initial begin
+    always_ff @(posedge clk or posedge rst) begin
-        pc = {(2**width){1'b0}};
+        if (rst) begin
-    end
+            pc <= {(2**width){1'b0}};
-
+        end else if (we) begin
-    always_ff @(posedge clk) begin
-        if (we) begin
             pc <= W;
         end else begin
             pc <= pc + 4;

modules/ram.sv

@@ -2,7 +2,7 @@
 `define RAM_H
 
 module ram #(addrwidth=9, datawidth=5)(
-    input logic [0:0] clk,
+    input logic [0:0] clk, input logic [0:0] rst,
     input logic [addrwidth-1:0] addr,
     input logic [0:0] we,
     input logic [datawidth-1:0] data_in,
@@ -12,15 +12,12 @@ module ram #(addrwidth=9, datawidth=5)(
     // TODO: Make this byte-sized, NOT word-sized!
     logic [2**datawidth-1:0] mem[0:255];
 
-    // NOTE: Possible issue with assignments still pending by end of initial block
-    initial begin
-        for (integer ADDR = 0; ADDR < 256; ADDR = ADDR + 1) begin
-            mem[ADDR] <= 32'b0;
-        end
-    end
-
     always_ff @(posedge clk) begin
-        if (we) begin
+        if (rst) begin
+            for (integer ADDR = 0; ADDR < 256; ADDR = ADDR + 1) begin
+                mem[ADDR] <= 32'b0;
+            end
+        end else if (we) begin
             mem[addr] <= data_in;
         end
     end

tests/mips.sv

@@ -15,13 +15,20 @@
 
 module mips_tb();
     logic [0:0] clk;
-    assignment2 #(5) CPU (clk);
+    logic [0:0] rst;
+    assignment2 #(5) CPU (clk, rst);
 
     initial clk = 0;
+    initial rst = 0;
     always #1 clk = ~clk;
 
     integer num_errors = 0;
     initial begin
+        rst = 1;
+        #2;
+        rst = 0;
+        #2;
+        
         $dumpfile("output.vcd");
 		$dumpvars(0, clk);
 		$dumpvars(1, CPU.REGS);
@@ -31,6 +38,7 @@ module mips_tb();
 		$dumpvars(5, CPU.CONTROL_UNIT);
 		$dumpvars(5, CPU.instruction);
 		$dumpvars(5, CPU.ALU);
+		$dumpvars(6, CPU.flags);
 
         // Zero out lower registers
         $display("Beginning MIPS tests");