diff --git a/tests/alu_tb.sv b/tests/alu_tb.sv
index 282d5c9..fd7d300 100644
--- a/tests/alu_tb.sv
+++ b/tests/alu_tb.sv
@@ -1,6 +1,38 @@
-// TODO: Both the ALU and this test bench is incomplete
 `#include "alu.sv"
 
-module alu_tb #(width=8)();
+module alu_tb #(width=2)();
+    logic [3:0] op_in;
+    logic [2**width-1:0] A_in;
+    logic [2**width-1:0] B_in;
+    logic [2**width-1:0] Y_out;
+    logic [1:0] flags_out;
 
+    logic [3:0] ops[1];
+    logic [2**width-1:0] A_cases[$size(ops)];
+    logic [2**width-1:0] B_cases[$size(ops)];
+    logic [2**width-1:0] Y_exp[$size(ops)];
+    logic [1:0] flags_exp[$size(ops)];
+
+    alu #(width)(op_in, A_in, B_in, Y_out, flags_out);
+
+    integer error_count;
+    initial begin
+
+
+        error_count = 0;
+        $display("Beginning ALU tests");
+        for (integer N = 0; N < $size(ops); ++N) begin
+            op = ops[N];
+            A_in = A_cases[N];
+            B_in = B_cases[N];
+            #1;
+            if (Y_out != Y_exp[N]) begin
+                $display("\t\x1b[38;5;9mALU Instruction 0b%b produced 0b%b_%b but 0b%b_%b was expected\x1b[m", op, flags_out, Y_out, flags_exp[N], Y_exp[N]);
+                error_count = error_count + 1;
+            end
+        end
+
+        if (error_count == 0) $display("\x1b[38;5;10mAll ALU tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d ALU test(s) failing\x1b[m", error_count);
+    end
 endmodule
\ No newline at end of file