diff --git a/modules/instruction_classifier.sv b/modules/instruction_classifier.sv
index 07c3ff1..e0a31f7 100644
--- a/modules/instruction_classifier.sv
+++ b/modules/instruction_classifier.sv
@@ -1,4 +1,4 @@
-module instruction_classifier(input logic op[5:0],
+module instruction_classifier(input logic[5:0] op,
     output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
     output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
     output logic[0:0] M);
diff --git a/tests/instruction_classifier_tb.sv b/tests/instruction_classifier_tb.sv
index 4d54943..0b5a968 100644
--- a/tests/instruction_classifier_tb.sv
+++ b/tests/instruction_classifier_tb.sv
@@ -1 +1,53 @@
-`#include "instruction_classifier.sv"
+`include "instruction_classifier.sv"
+module instruction_classifier_tb();
+    logic [5:0] op;
+    logic [6:0] C;
+    logic [5:0] ops[12];
+    logic [6:0] C_exp[12];
+
+    instruction_classifier dut(op, C[0:0], C[1:1], C[2:2], C[3:3], C[4:4], C[5:5], C[6:6]);
+
+    integer error_count;
+    initial begin
+        ops[0] = 6'b000000;
+        C_exp[0] = 7'b1000000;
+        ops[1] = 6'b000001;
+        C_exp[1] = 7'b0100000;
+        ops[2] = 6'b000010;
+        C_exp[2] = 7'b0010000;
+        ops[3] = 6'b000100;
+        C_exp[3] = 7'b0001000;
+        ops[4] = 6'b001000;
+        C_exp[4] = 7'b0000100;
+        ops[5] = 6'b010000;
+        C_exp[5] = 7'b0000010;
+        ops[6] = 6'b100000;
+        C_exp[6] = 7'b0000001;
+
+        ops[7] = 6'b000011;
+        C_exp[7] = 7'b0010000;
+        ops[8] = 6'b000101;
+        C_exp[8] = 7'b0001000;
+        ops[9] = 6'b001001;
+        C_exp[9] = 7'b0000100;
+        ops[10] = 6'b010001;
+        C_exp[10] = 7'b0000010;
+        ops[11] = 6'b100001;
+        C_exp[11] = 7'b0000001;
+
+        error_count = 0;
+        $display("Beginning Instruction Classifier tests");
+        for (integer N = 0; N < $size(ops); ++N) begin
+            op = ops[N];
+            #1;
+            if (C != C_exp[N]) begin
+                $display("\t\x1b[38;5;9mInstruction 0b%b produced 0b%b but 0b%b was expected\x1b[m", op, C, C_exp[N]);
+                error_count = error_count + 1;
+            end
+            $display("\tInstruction 0b%b produced 0b%b when 0b%b was expected", op, C, C_exp[N]);
+        end
+        if (error_count == 0) $display("\x1b[38;5;10mAll Instruction Classifier tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d Instruction Classifier test(s) failing\x1b[m", error_count);
+    end
+
+endmodule
\ No newline at end of file
diff --git a/tests/tests.sv b/tests/tests.sv
index 892382c..46ea98f 100644
--- a/tests/tests.sv
+++ b/tests/tests.sv
@@ -1,3 +1,4 @@
 `include "tests/seven_seg_tb.sv"
 `include "tests/lu_tb.sv"
-`include "tests/asu_tb.sv"
\ No newline at end of file
+`include "tests/asu_tb.sv"
+`include "tests/instruction_classifier_tb.sv"
\ No newline at end of file