diff --git a/asm/bin/ELEC4720-2026s2-Ass-03-HazardsDemo.hex b/asm/bin/ELEC4720-2026s2-Ass-03-HazardsDemo.hex new file mode 100644 index 0000000..25006fa --- /dev/null +++ b/asm/bin/ELEC4720-2026s2-Ass-03-HazardsDemo.hex @@ -0,0 +1,18 @@ +01084023 +25090007 +ad090000 +8d0a0000 +012a5821 +012b6022 +212d0003 +018d7020 +012d8024 +012d8825 +012d9026 +012d9827 +018ea02a +018ea82b +25080001 +010db02b +12d4fffd +12d6ffff \ No newline at end of file diff --git a/asm/bin/ELEC4720-2026s2-Ass-03-HazardsDemo.txt b/asm/bin/ELEC4720-2026s2-Ass-03-HazardsDemo.txt new file mode 100644 index 0000000..5dd4b69 --- /dev/null +++ b/asm/bin/ELEC4720-2026s2-Ass-03-HazardsDemo.txt @@ -0,0 +1,51 @@ +// $File: NewcastleUniversity/ELEC4720/2026s2/src/Code/Assignment/Ass-03-HazardsDemo.txt $ +// $Date: 2026-10-29 14:44:32 +1100 (Thu, 29 Oct 2026) $ +// $Revision: 2531 $ +// $Author: Peter $ +// +// Course: ELEC4720(2026s2) Programmable Logic Design +// School: Engineering +// University: The University of Newcastle +// Address: CALLAGHAN NSW 2308 Australia +// +// Author: Dr Peter Stepien +// Email: peter.stepien@newcastle.edu.au +// Copyright: 2026 + +// Assignment 3 Demonstration Program (with hazards) + +// main: +// Initialise some registers +01084023 // subu $t0, $t0, $t0 +25090007 // addiu $t1, $t0, 7 + +// Memory operations +ad090000 // sw $t1, 0x0000($t0) +8d0a0000 // lw $t2, 0x0000($t0) + +// Remaining arithmetic +012a5821 // addu $t3, $t1, $t2 +012b6022 // sub $t4, $t1, $t3 +212d0003 // addi $t5, $t1, 3 +018d7020 // add $t6, $t4, $t5 + +// Logical +012d8024 // and $s0, $t1, $t5 +012d8825 // or $s1, $t1, $t5 +012d9026 // xor $s2, $t1, $t5 +012d9827 // nor $s3, $t1, $t5 + +// Comparison +018ea02a // slt $s4, $t4, $t6 +018ea82b // sltu $s5, $t4, $t6 + +// Loop to test branch +// loop: +25080001 // addiu $t0, $t0, 1 +010db02b // sltu $s6, $t0, $t5 +12d4fffd // beq $s6, $s4, loop + +// Endless loop at end of program (FPGA) +// finish: +12d6ffff // beq $s6, $s6, finish + diff --git a/asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.hex b/asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.hex new file mode 100644 index 0000000..40be812 --- /dev/null +++ b/asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.hex @@ -0,0 +1,34 @@ +01084023 +01294823 +014a5023 +016b5823 +25090007 +ad090000 +014a5023 +016b5823 +018c6023 +8d0a0000 +016b5823 +018c6023 +01ad6823 +012a5821 +018c6023 +01ad6823 +01ce7023 +012b6022 +212d0003 +01ce7023 +01ef7823 +02108023 +018d7020 +012d8024 +012d8825 +012d9026 +012d9827 +018ea02a +018ea82b +1211ffff +1211fffe +1211fffd +1211fffc +12d6ffff diff --git a/asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.txt b/asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.txt new file mode 100644 index 0000000..c7916f5 --- /dev/null +++ b/asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.txt @@ -0,0 +1,50 @@ +// $File: NewcastleUniversity/ELEC4720/2026s2/src/Code/Assignment/Ass-03-NoHazardsDemo.txt $ +// $Date: 2026-10-29 14:44:32 +1100 (Thu, 29 Oct 2026) $ +// $Revision: 2531 $ +// $Author: Peter $ +// +// Course: ELEC4720(2026s2) Programmable Logic Design +// School: Engineering +// University: The University of Newcastle +// Address: CALLAGHAN NSW 2308 Australia +// +// Author: Dr Peter Stepien +// Email: peter.stepien@newcastle.edu.au +// Copyright: 2026 + +// Assignment 3 Demonstration Program (without hazards) + +01084023 +01294823 +014a5023 +016b5823 +25090007 +ad090000 +014a5023 +016b5823 +018c6023 +8d0a0000 +016b5823 +018c6023 +01ad6823 +012a5821 +018c6023 +01ad6823 +01ce7023 +012b6022 +212d0003 +01ce7023 +01ef7823 +02108023 +018d7020 +012d8024 +012d8825 +012d9026 +012d9827 +018ea02a +018ea82b +1211ffff +1211fffe +1211fffd +1211fffc +12d6ffff diff --git a/asm/src/ELEC4720-2026s2-Ass-03-HazardsDemo.s b/asm/src/ELEC4720-2026s2-Ass-03-HazardsDemo.s new file mode 100644 index 0000000..90f9c19 --- /dev/null +++ b/asm/src/ELEC4720-2026s2-Ass-03-HazardsDemo.s @@ -0,0 +1,61 @@ +# $File: NewcastleUniversity/ELEC4720/2026s2/src/Code/Assignment/Ass-02-Demo.s $ +# $Date: 2026-10-07 01:54:03 +1100 (Wed, 07 Oct 2026) $ +# $Revision: 2525 $ +# $Author: Peter $ +# +# Course: ELEC4720(2026s2) Programmable Logic Design +# School: Engineering +# University: The University of Newcastle +# Address: CALLAGHAN NSW 2308 Australia +# +# Author: Dr Peter Stepien +# Email: peter.stepien@newcastle.edu.au +# Copyright: 2026 + +# Assignment 3 Demonstration Program (with hazards) + + .text + .globl main + .globl loop + .globl finish + +main: + # Initialise some registers + subu $t0, $t0, $t0 # Set t0 = 0 (R8, modified below) + addiu $t1, $t0, 7 # Set t1 = 7 (R9) + + # Memory operations + sw $t1, 0x10000000($t0) # Save t1 to memory (change to 0x0000 for FPGA) + lw $t2, 0x10000000($t0) # Load t2 from memory (change to 0x0000 for FPGA) (R10) + + # Remaining arithmetic + addu $t3, $t1, $t2 # Unsigned t3 = t1 + t2 = 14 (R11) + sub $t4, $t1, $t3 # Signed t4 = t1 - t3 = -7 (R12) + addi $t5, $t1, 3 # Signed t5 = t1 + 3 = 10 (R13) + add $t6, $t4, $t5 # Signed t6 = t4 + t5 = 3 (R14) + + # Logical (t1 = 0000..0111, t5 = 0000..1010) + and $s0, $t1, $t5 # s0 = t1 and t5 = 2 (0000..0010) (R16) + or $s1, $t1, $t5 # s1 = t1 or t5 = 15 (0000..1111) (R17) + xor $s2, $t1, $t5 # s2 = t1 xor t5 = 13 (0000..1101) (R18) + nor $s3, $t1, $t5 # s3 = t1 nor t5 = -16 (1111..0000) (R19) + + # Comparison + slt $s4, $t4, $t6 # Signed s4 = t4 < t6 = 1 (true) (R20) + sltu $s5, $t4, $t6 # Unsigned s5 = t4 < t6 = 0 (false) (R21) + + # Loop to test branch +loop: + addiu $t0, $t0, 1 # Increment counter + sltu $s6, $t0, $t5 # Unsigned s6 = t0 < t5 (Last 0) (R22) + beq $s6, $s4, loop # Loop if s6 == s4 + + # Endless loop at end of program (FPGA) +finish: + # beq $s6, $s6, finish # Endless loop + + # Alternative system call to exit program (spim) + li $v0, 10 + syscall + +# END OF FILE diff --git a/asm/src/ELEC4720-2026s2-Ass-03-NoHazardsDemo.s b/asm/src/ELEC4720-2026s2-Ass-03-NoHazardsDemo.s new file mode 100644 index 0000000..15b65cd --- /dev/null +++ b/asm/src/ELEC4720-2026s2-Ass-03-NoHazardsDemo.s @@ -0,0 +1,77 @@ +# $File: NewcastleUniversity/ELEC4720/2026s2/src/Code/Assignment/Ass-02-Demo.s $ +# $Date: 2026-10-07 01:54:03 +1100 (Wed, 07 Oct 2026) $ +# $Revision: 2525 $ +# $Author: Peter $ +# +# Course: ELEC4720(2026s2) Programmable Logic Design +# School: Engineering +# University: The University of Newcastle +# Address: CALLAGHAN NSW 2308 Australia +# +# Author: Dr Peter Stepien +# Email: peter.stepien@newcastle.edu.au +# Copyright: 2026 + +# Assignment 3 Demonstration Program (without hazards) + + .text + .globl main + .globl loop + .globl finish + +main: + # Set registers to zero + subu $t0, $t0, $t0 # Set t0 = 0 (R8) + subu $t1, $t1, $t1 # Set t1 = 0 + subu $t2, $t2, $t2 # Set t2 = 0 + subu $t3, $t3, $t3 # Set t3 = 0 + addiu $t1, $t0, 7 # Set t1 = 7 (R9) + + # Memory operations + sw $t1, 0x10000000($t0) # Save t1 to memory (change to 0x0000 for FPGA) + subu $t2, $t2, $t2 # Set t2 = 0 + subu $t3, $t3, $t3 # Set t3 = 0 + subu $t4, $t4, $t4 # Set t4 = 0 + lw $t2, 0x10000000($t0) # Load t2 from memory (change to 0x0000 for FPGA) (R10) + subu $t3, $t3, $t3 # Set t3 = 0 + subu $t4, $t4, $t4 # Set t4 = 0 + subu $t5, $t5, $t5 # Set t5 = 0 + + # Remaining arithmetic + addu $t3, $t1, $t2 # Unsigned t3 = t1 + t2 = 14 (R11) + subu $t4, $t4, $t4 # Set t4 = 0 + subu $t5, $t5, $t5 # Set t5 = 0 + subu $t6, $t6, $t6 # Set t6 = 0 + sub $t4, $t1, $t3 # Signed t4 = t1 - t3 = -7 (R12) + addi $t5, $t1, 3 # Signed t5 = t1 + 3 = 10 (R13) + subu $t6, $t6, $t6 # Set t6 = 0 + subu $t7, $t7, $t7 # Set t7 = 0 + subu $s0, $s0, $s0 # Set s0 = 0 + add $t6, $t4, $t5 # Signed t6 = t4 + t5 = 3 (R14) + + # Logical (t1 = 0000..0111, t5 = 0000..1010) + and $s0, $t1, $t5 # s0 = t1 and t5 = 2 (0000..0010) (R16) + or $s1, $t1, $t5 # s1 = t1 or t5 = 15 (0000..1111) (R17) + xor $s2, $t1, $t5 # s2 = t1 xor t5 = 13 (0000..1101) (R18) + nor $s3, $t1, $t5 # s3 = t1 nor t5 = -16 (1111..0000) (R19) + + # Comparison + slt $s4, $t4, $t6 # Signed s4 = t4 < t6 = 1 (true) (R20) + sltu $s5, $t4, $t6 # Unsigned s5 = t4 < t6 = 0 (false) (R21) + + # Never branches (need to manually stop program for Q1) +loop: + beq $s0, $s1, loop # Loop if s0 == s1 + beq $s0, $s1, loop # Loop if s0 == s1 + beq $s0, $s1, loop # Loop if s0 == s1 + beq $s0, $s1, loop # Loop if s0 == s1 + + # Endless loop at end of program (FPGA) +finish: + # beq $s6, $s6, finish # Endless loop + + # Alternative system call to exit program (spim) + li $v0, 10 + syscall + +# END OF FILE